Data Processing System With Networked Instruction Memory
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Solution Overview
Problem
In data processing systems, the remoteness of data memory from the processor increases data access time, slowing down performance for data-intensive applications, and existing architectures struggle to efficiently share instructions among multiple networked processors.
Innovation Solution
The method involves selecting a data unit in a local data memory, identifying an appropriate instruction from a remote instruction memory based on its characteristics, and requesting it through a data network for execution by the processor, allowing for efficient sharing of instructions among multiple processors and optimizing execution cycles and priority levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data memory is placed remotely to enable networked access and instruction sharing, then instruction sharing efficiency is improved, but data access time increases
Solution Approach 1:
The system segments memory into separate data memory and instruction memory components, with instruction memory specifically designated for networked access and sharing among multiple processors. This segmentation allows data memory to remain locally optimized for fast access while instruction memory is optimized for networked sharing, resolving the contradiction between local access speed and remote sharing efficiency.
Solution Approach 2:
The patent introduces an intermediary instruction memory component that acts as a buffer between the processor and remote data memory. This intermediary allows processors to share instructions efficiently over the network while the actual data operations can proceed with optimized access patterns, mediating between the needs for fast local access and efficient networked sharing.
2Adaptability or versatility
If instructions are fetched from remote memory, then instruction sharing among multiple processors is enabled, but processing speed decreases
Solution Approach 1:
The system performs preliminary actions by pre-fetching and caching frequently accessed instructions in local instruction memory before they are needed for execution. This preliminary action reduces the need for processors to wait for remote instruction fetches, maintaining processing speed while still enabling instruction sharing among multiple processors through the networked instruction memory architecture.
Solution Approach 2:
The patent implements local quality by providing each processor with local instruction memory that is optimized for its specific needs, while still allowing access to remote shared instruction memory. This local optimization ensures that each processor has fast access to its frequently used instructions, maintaining high processing speed while the remote instruction memory enables sharing capabilities across the network.
3Speed
If data memory is local to processor, then data access speed is improved, but instruction sharing among networked processors becomes inefficient
Solution Approach 1:
The system segments the memory architecture into local data memory for fast processor access and separate networked instruction memory for efficient sharing. This segmentation allows each component to be optimized for its specific function - data memory for speed and instruction memory for sharing efficiency - resolving the contradiction between local access speed and networked sharing capability.
Solution Approach 2:
The patent creates a universal instruction memory system that serves multiple processors simultaneously through the network, while each processor maintains its own local data memory for fast access. This multi-functional architecture allows the instruction memory to serve as a shared resource across multiple processors, enabling efficient instruction sharing without compromising the local data access speed of individual processors.
Data Source
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AI summary
Some methods, computer program products, and data processing nodes identify a data unit in a data memory that is to be operated upon by a processor circuit, and uses a characteristic of the data unit to identify what instruction(s) within an instruction memory is be executed by the processor circuit to perform an operation upon the data unit. The data memory may be local to the processor circuit, and the instruction memory may be remotely accessible to the processor circuit through a data network.