Neural Network Architecture Estimation for Circuit Size and Delay
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Solution Overview
Problem
Existing techniques for generating neural network architectures fail to minimize circuit size, leading to inadequate evaluation of processing time and circuit size requirements, which is critical as AI processing circuits become heavier and larger.
Innovation Solution
An architecture estimation device that receives neural network information and non-functional requirements to generate and search for architecture combinations that reduce delay, determining candidates that satisfy these requirements, thereby enabling precise evaluation of circuit architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing techniques for generating neural network architectures are used, then processing time requirements can be met, but circuit size is not minimized
Solution Approach 1:
The patent applies parameter changes by systematically varying architectural parameters (number of neurons per layer, number of layers, activation functions, connectivity patterns) to find optimal configurations that simultaneously satisfy processing time requirements and minimize circuit size. The estimation device evaluates multiple parameter combinations to identify architectures that achieve the best trade-off between speed and size.
Solution Approach 2:
The patent employs dynamic adjustment of architectural parameters based on performance requirements. The system dynamically selects and adjusts parameters such as layer depths, neuron counts, and connectivity structures to optimize the balance between processing speed and circuit size, rather than using fixed architectural configurations.
2Reliability
If neural network architectures are optimized for processing speed, then non-functional requirements may be satisfied, but circuit size increases
Solution Approach 1:
The patent uses parameter changes to adjust architectural characteristics while maintaining satisfaction of non-functional requirements. By systematically modifying parameters such as the number of layers, neurons per layer, and connectivity patterns, the system finds configurations that meet processing time and accuracy requirements while minimizing circuit size.
Solution Approach 2:
The patent applies partial action by selecting only the necessary number of layers and neurons required to meet non-functional requirements, rather than using excessive capacity. This approach ensures that the circuit size is minimized while still achieving the required processing performance and reliability.
3Weight of stationary object
If comprehensive architecture search is performed to find optimal configurations, then circuit size minimization is achieved, but estimation time increases
Solution Approach 1:
The patent applies preliminary action by pre-defining a search space of plausible architectural configurations and pre-establishing evaluation criteria. The estimation device uses pre-computed performance models and constraints to guide the search, avoiding exhaustive exploration of all possible architectures and thus reducing estimation time while still finding optimal configurations.
Solution Approach 2:
The patent efficiently explores architectural space by systematically varying key parameters (layer count, neuron counts, connectivity patterns) within defined ranges. This structured parameter exploration allows comprehensive evaluation of meaningful configurations without requiring exhaustive search, balancing estimation time with optimization quality.
Data Source
AI summary
A reception unit (110) receives NN information (151) and non-functional requirements (152) demanded for a circuit. A search unit (120) generates combinations of interlayer architectures and intra-layer architectures as architecture combinations (121). Then, the search unit (120) searches for a plurality of architecture combination candidates (122) that reduce an amount of delay as the non-functional requirements, from among the architecture combinations (121). A determination unit (130) determines whether each of the plurality of architecture combination candidates (122) satisfies the non-functional requirements (152) or not. A candidate information generation unit (140) generates candidate information (154) including architecture candidates (131) that satisfy the non-functional requirements among the plurality of architecture combination candidates (122).