Neural Arithmetic Circuit With Bit-Level Redundancy for Reliability

Solution Overview

Problem

Arithmetic processing devices for neural networks face challenges in reducing circuit area and power consumption while maintaining reliability, as simple multiplexing leads to increased circuit area and power consumption due to the need for many arithmetic units.

Innovation Solution

Implementing redundancy in specific parts of bits, such as high-order bits, of weighting coefficients and input data, with a majority voting system to enhance reliability without increasing power consumption and circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If simple multiplexing is implemented to enhance reliability of arithmetic operations, then reliability is improved, but circuit area and power consumption increase

Engineering Contradiction:

Improvereliability of arithmetic operationsVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the bit representation into two distinct parts: a first part (high-order bits) and a second part (low-order bits). This segmentation allows different redundancy strategies to be applied to each part, rather than treating all bits uniformly. The first part uses higher redundancy for reliability, while the second part uses lower redundancy to save circuit area and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different redundancy levels to different parts of the bit representation. Specifically, the high-order bits (first part) are given higher redundancy through multiple arithmetic units, while the low-order bits (second part) use fewer arithmetic units. This localized differentiation optimizes the balance between reliability and resource consumption.

Inventive Principle:

Principle #3Local quality

2Reliability

If simple multiplexing is implemented to enhance reliability of arithmetic operations, then reliability is improved, but power consumption increases

Engineering Contradiction:

Improvereliability of arithmetic operationsVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent segments the bit representation into two distinct parts: a first part (high-order bits) and a second part (low-order bits). This segmentation allows different redundancy strategies to be applied to each part, rather than treating all bits uniformly. The first part uses higher redundancy for reliability, while the second part uses lower redundancy to save circuit area and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different redundancy levels to different parts of the bit representation. Specifically, the high-order bits (first part) are given higher redundancy through multiple arithmetic units, while the low-order bits (second part) use fewer arithmetic units. This localized differentiation optimizes the balance between reliability and resource consumption.

Inventive Principle:

Principle #3Local quality

3Reliability

If many arithmetic units are used to perform reliable arithmetic operations, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvereliability of arithmetic operationsVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the bit representation into two distinct parts: a first part (high-order bits) and a second part (low-order bits). This segmentation allows different redundancy strategies to be applied to each part, rather than treating all bits uniformly. The first part uses higher redundancy for reliability, while the second part uses lower redundancy to save circuit area and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different redundancy levels to different parts of the bit representation. Specifically, the high-order bits (first part) are given higher redundancy through multiple arithmetic units, while the low-order bits (second part) use fewer arithmetic units. This localized differentiation optimizes the balance between reliability and resource consumption.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10817773B2Arithmetic processing device and arithmetic processing method

Publication Date: 2020.10.27 SONY GROUP CORP

AI summary

The present technology relates to an arithmetic processing device and an arithmetic processing method that enable the reduction of a circuit area while lowering power consumption, in performing more reliable arithmetic operations of a neural network.In arithmetic operations of the neural network, the arithmetic processing device makes a specific part of bits of a weighting coefficient and input data used for the arithmetic operations redundant such that redundancy of the specific part of bits becomes larger than redundancy of remaining bits except the specific part of bits, thereby being able to reduce the circuit area while lowering the power consumption in performing reliable arithmetic operations of the neural network. The present technology can be applied to, for example, an arithmetic processing device configured to perform arithmetic operations of a neural network.