Neural Network Bit-Segmented Computing for Precise Edge Inference
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Solution Overview
Problem
Existing neural network devices face challenges in performing precise calculations due to size limitations when implemented as edge computing devices, particularly with neuromorphic chips, which require high-resolution memory cells and digital-to-analog converters that increase device size and cost.
Innovation Solution
A neural network device incorporating a digital-to-analog converter, a cell array with memory cells, and an analog-to-digital converter, along with a processor, to manage bit resolution and perform operations efficiently, allowing for precise calculations without excessive size or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution memory cells and digital-to-analog converters are used in neuromorphic chips, then calculation precision is improved, but device size and cost increase
Solution Approach 1:
The input signal is divided into multiple segments corresponding to different bit positions. Each segment is processed separately through the memory cell array, and the results are combined to form the final output. This segmentation allows the system to achieve high-precision calculations using lower-resolution individual components.
Solution Approach 2:
The patent transitions from processing high-resolution signals in a single dimension to processing multiple low-resolution signal segments in parallel across different time slots or channels. By adding the time dimension for sequential processing of segments, the system achieves equivalent precision without requiring high-resolution hardware components.
2Measurement precision
If high-resolution memory cells and digital-to-analog converters are used in neuromorphic chips, then calculation precision is improved, but device cost increases
Solution Approach 1:
The patent uses lower-resolution, cheaper memory cells and digital-to-analog converters instead of expensive high-resolution components. By processing multiple segments sequentially and combining results computationally, the system achieves high precision using inexpensive hardware building blocks.
Solution Approach 2:
The patent changes the resolution parameter of the hardware components from high to low, compensating for the reduced hardware precision through software-based segment processing and combination. This parameter change reduces manufacturing cost while maintaining calculation precision through algorithmic compensation.
3Measurement precision
If more bits of input signal are processed, then calculation precision is improved, but the number of required digital-to-analog converter bits increases device complexity
Solution Approach 1:
The high-bit input signal is segmented into multiple lower-bit groups. Each segment is converted by the digital-to-analog converter with lower bit resolution, reducing the DAC complexity requirement while maintaining overall precision through the combination of multiple segment results.
Solution Approach 2:
The input signal is pre-processed into segments before being fed to the digital-to-analog converter. This preliminary segmentation allows the use of lower-resolution DACs, as each segment requires fewer bits, thereby reducing device complexity while preserving the ability to represent high-precision values through combination.
Data Source
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AI summary
A neural network device includes: a digital-to-analog converter configured to convert a digital input to an analog input of either voltage or current; a cell array including a plurality of memory cells arranged in a plurality of bit lines and a plurality of word lines and configured to store a weight of a neural network, and configured to perform an operation on the analog input that is input through the word lines and output an analog output of any one of current and voltage, through the bit lines; an analog-to-digital converter configured to convert the analog output into a digital output; and at least one processor electrically connected to the digital-to-analog converter and the analog-to-digital converter and configured to control the digital input and the digital output.