Neural-Network CDR Circuit for Large-Jitter Signal Locking
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Solution Overview
Problem
Existing clock and data recovery (CDR) systems struggle to lock the phase and frequency of input signals with large jitter, leading to poor performance.
Innovation Solution
A CDR circuit utilizing a neural network circuit to generate information on the frequency difference between a reference clock signal and an input signal, allowing the CDR to adjust the clock signal's phase or frequency effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CDR measures data transitions continuously to control phase, then the CDR can maintain phase control under normal conditions, but the CDR cannot lock phase and frequency when input signal has large jitter
Solution Approach 1:
The patent introduces a neural network circuit as an intermediary between the phase detector and the phase-locked loop. This neural network processes phase detection results to generate frequency difference information, which then controls the voltage-controlled oscillator. This intermediary structure enables the system to handle large jitter conditions that conventional direct measurement cannot manage.
Solution Approach 2:
The patent changes the parameter being measured from direct phase transitions to frequency difference information derived from multiple phase detection results. By using the neural network to analyze patterns in phase detection data and extract frequency difference parameters, the system can lock onto signals with large jitter that would otherwise be unmanageable.
2Reliability
If a conventional CDR uses direct phase measurement, then the structure remains simple, but the system fails to lock when input signal quality degrades
Solution Approach 1:
The neural network circuit serves as an intermediary processing layer that enhances the CDR's ability to handle degraded signals. While this adds circuit complexity, it dramatically improves reliability under adverse conditions such as large jitter, creating a trade-off that favors performance in challenging environments.
3Measurement precision
If the CDR continuously measures data transitions to control phase, then phase control is maintained under normal conditions, but frequency locking fails under large jitter conditions
Solution Approach 1:
The neural network circuit performs preliminary processing on phase detection results before they are used for frequency control. By pre-processing the raw phase detection data to extract frequency difference information, the system prepares more reliable control signals that enable successful frequency locking even when input signals exhibit large jitter.
Solution Approach 2:
The system uses feedback from multiple phase detection results processed by the neural network to generate frequency difference information. This feedback mechanism allows the VCO to adjust its output based on accumulated phase detection patterns, improving frequency locking reliability under challenging signal conditions.
Data Source
AI summary
The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.