Neural Network Chip Architecture With Compression Mapping Circuits
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Solution Overview
Problem
Existing neural network computations are inefficient due to high power consumption and computation requirements, as they rely on CPUs or GPUs, which are not optimized for the specific operations of neural networks.
Innovation Solution
An integrated circuit chip device with a primary processing circuit and multiple basic processing circuits arranged in an array, where the basic processing circuits perform compression mapping on data, reducing the need for extensive computation and data transmission, and allowing for efficient neural network operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CPU or GPU is used to implement neural network operations, then the device can perform general-purpose computation, but power consumption and computation requirements become excessively high
Solution Approach 1:
The processing system is segmented into a primary processing circuit and multiple basic processing circuits arranged in an array. Each basic processing circuit is connected to adjacent circuits and can be selectively activated, dividing the computation task across multiple specialized units rather than using a single general-purpose processor, thereby reducing overall power consumption while maintaining computational capability
Solution Approach 2:
The patent implements local quality by creating specialized processing units with different functions (compression mapping circuits, basic processing circuits) positioned at specific locations in the array. Each unit is optimized for its specific function, allowing the system to perform neural network operations with lower power consumption compared to general-purpose CPUs or GPUs
2Adaptability or versatility
If CPU or GPU is used to implement neural network operations, then the device can handle complex computations, but the processing speed and efficiency are insufficient
Solution Approach 1:
The compression mapping circuits perform preliminary compression on input data before it reaches the basic processing circuits. This preliminary action reduces the amount of data that needs to be processed in subsequent stages, thereby increasing processing speed and efficiency without sacrificing computation capability
Solution Approach 2:
The basic processing circuits are arranged in an array with each circuit connected to adjacent circuits, enabling continuous data flow and parallel processing. Multiple circuits can operate simultaneously on different portions of the neural network computation, maintaining continuous useful action and improving overall processing speed
3Ease of operation
If data is transmitted extensively between processing units, then complete neural network operations can be performed, but transmission resources and computing resources are wasted
Solution Approach 1:
The computation is segmented across the array of basic processing circuits, with each circuit handling specific portions of the neural network operations. This segmentation reduces the amount of data that needs to be transmitted between units, as each unit processes only its assigned portion locally before passing results to adjacent units
Solution Approach 2:
The compression mapping circuits act as intermediaries that compress data before transmission to basic processing circuits. This intermediary function reduces the volume of data transmitted across the system, conserving transmission resources and reducing energy loss
Data Source
AI summary
The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.