Neural Network Chip Partitioning With Fixed-Point Computation
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Solution Overview
Problem
Existing neural network computations on CPU or GPU require high power consumption and large amounts of computations, which are inefficient.
Innovation Solution
An integrated circuit chip apparatus with a main processing circuit and multiple basic processing circuits, capable of converting data between floating point and fixed point types, partitions data for distributed computation, reducing the amount of computations and power consumption by utilizing fixed point operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If neural network computations are performed on CPU or GPU, then the computations can be executed, but the power consumption is high and the computational efficiency is low
Solution Approach 1:
The patent segments the processing circuit into multiple independent processing units, each capable of performing neural network computations. This segmentation allows parallel processing of different data blocks, significantly improving computational efficiency while reducing the power consumption per unit compared to centralized CPU/GPU processing.
Solution Approach 2:
The patent changes the data representation parameter from floating-point to fixed-point format for neural network computations. This parameter change reduces the computational complexity and power consumption while maintaining sufficient accuracy for neural network operations, directly addressing the high power consumption issue of traditional CPU/GPU processing.
2Measurement precision
If floating point data type is used for neural network computations, then the precision is maintained, but the amount of computations increases
Solution Approach 1:
The patent changes the data type parameter from floating-point to fixed-point representation. This parameter change reduces the computational load by eliminating complex floating-point operations while maintaining sufficient precision for neural network applications through carefully designed fixed-point formats and quantization schemes.
Data Source
AI summary
An integrated circuit chip apparatus and a processing method performed by an integrated circuit chip apparatus are disclosed. The disclosed integrated circuit chip apparatus and processing method are used for executing a multiplication operation, a convolution operation, or a training operation of a neural network. The present technical solution has the advantages of a reduced computational cost and low power consumption.