Neural Network Chip Architecture With Mixed-Precision Parallel Computing
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Solution Overview
Problem
Existing neural network computations on CPU or GPU require significant computational resources and consume high power due to the large amount of computations involved.
Innovation Solution
An integrated circuit chip apparatus with a main processing circuit and multiple basic processing circuits, where data type conversion between floating point and fixed point data types is performed, allowing for parallel and series neural network computations to reduce computational load and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If neural network computations are performed on CPU or GPU, then computational capability is provided, but power consumption and computational load are high
Solution Approach 1:
The system segments neural network computations into two distinct types: first set computations (e.g., convolution operations) executed by dedicated first processing circuits, and second set computations (e.g., fully connected layer operations) executed by general-purpose second processing circuits. This segmentation allows each processing unit to be optimized for its specific task, reducing overall power consumption while maintaining computational capability.
Solution Approach 2:
The system dynamically changes computational parameters by selecting different data types (floating-point or fixed-point) and different processing circuits based on the specific neural network operation being performed. This parameter adaptation enables the system to use lower-power fixed-point arithmetic and dedicated hardware circuits for appropriate operations, thereby reducing power consumption while maintaining accuracy.
2Measurement precision
If floating point data type is used for neural network computations, then computational precision is maintained, but computational complexity and power consumption increase
Solution Approach 1:
The system dynamically selects between floating-point and fixed-point data types based on the specific computational requirements of different neural network layers and operations. This dynamic adaptation allows the system to use floating-point precision only where necessary (maintaining accuracy) while using fixed-point arithmetic for operations where it suffices (reducing complexity and power consumption).
Solution Approach 2:
The system changes the precision parameter of data representations based on computational context. By adjusting the data type parameter (floating-point vs. fixed-point) according to the specific neural network operation, the system optimizes the balance between precision and computational complexity for each operation.
Data Source
AI summary
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.