Neural Network Chip Architecture for Low-Power Parallel Computing
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Solution Overview
Problem
Existing neural networks rely on CPU or GPU for computations, leading to high power consumption and inefficient processing of large computational demands.
Innovation Solution
An integrated circuit chip apparatus with a main processing circuit and multiple basic processing circuits, equipped with data type conversion circuits, performs neural network computations in parallel and series, reducing computational loads and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If neural network computations are performed using CPU or GPU, then the computations can be executed, but the power consumption is high and processing efficiency is low
Solution Approach 1:
The processor is divided into a master processing unit and multiple slave processing units. Each slave processing unit independently performs neural network computations on different data batches or layers, enabling parallel processing. This segmentation allows the system to distribute computational workload across multiple specialized units, significantly improving processing efficiency while reducing the power consumption per unit compared to using general-purpose CPU or GPU for the same task.
2Measurement precision
If a large number of computations are performed to achieve accurate neural network operations, then the computation accuracy is maintained, but the computational load and power consumption increase
Solution Approach 1:
Each slave processing unit is specifically designed and optimized for neural network computations, with dedicated computational resources and data structures tailored to this purpose. This local optimization allows each unit to perform computations efficiently with reduced redundancy, maintaining high accuracy while minimizing the overall computational load across the system.
Solution Approach 2:
The slave processing units continuously process neural network computations in parallel without idle time, maintaining constant useful action. Each unit processes data continuously through the neural network layers, eliminating the need for sequential processing and reducing total computational load while maintaining accuracy through continuous parallel computation.
Data Source
AI summary
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.