Neural Network Training Chip for 2D Vector and Tensor Computation
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Solution Overview
Problem
Existing neural network training methods are inefficient and not optimized for high-dimensional tensor computations and 32-bit precision, limiting performance in machine learning applications.
Innovation Solution
A special-purpose hardware chip designed with a scalar processor, vector processor, matrix multiply unit, and sparse computation core, optimized for high-dimensional tensor operations and 32-bit precision, featuring a 2D array of vector processing units and high-bandwidth memory, enabling efficient neural network training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If general-purpose processors are used for neural network training, then versatility is maintained, but computation speed and efficiency deteriorate
Solution Approach 1:
The processor is divided into multiple vector processing units (VPUs) arranged in a 2D array, where each VPU can independently execute vector operations. This segmentation enables parallel processing of neural network computations while maintaining manageable complexity through modular design
Solution Approach 2:
The patent transitions from traditional 1D vector processing to a 2D array of vector processing units, enabling simultaneous processing of multiple data elements across two dimensions. This dimensional expansion significantly increases computation throughput for high-dimensional tensor operations in neural networks
2Measurement precision
If 64-bit precision computation is used, then numerical accuracy is improved, but computation efficiency and power consumption worsen
Solution Approach 1:
The patent dynamically adjusts precision parameters based on computational requirements, supporting both 32-bit and 64-bit floating-point operations. For operations where full 64-bit precision is not critical, the system can operate in 32-bit mode to achieve better efficiency, while switching to 64-bit when higher accuracy is needed
3Productivity
If high-dimensional tensor operations are performed using conventional processors, then compatibility with existing software is maintained, but computation performance deteriorates
Solution Approach 1:
The patent introduces a tensor processing unit that acts as an intermediary between conventional processors and high-dimensional tensor operations. This specialized unit handles complex tensor computations efficiently while presenting a compatible interface to existing software, bridging the gap between legacy systems and advanced computational requirements
Data Source
AI summary
Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.