Neural Network Integrated Circuit with Barrel Shifter Data Handling
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Solution Overview
Problem
Existing artificial neural network integrated circuits are energy-intensive, complex, and inflexible in terms of parallelization due to high data handling requirements, leading to inefficient execution and bulky structure.
Innovation Solution
An integrated circuit design that includes separate memories for neural network parameters and input/output data, along with barrel shifter circuits for efficient data handling and a control unit to manage these components, allowing direct access and reducing the need for a bus, enabling rapid execution with lower energy consumption and parallelization capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional integrated circuits use shared bus for data access, then device complexity is reduced, but execution speed decreases and energy consumption increases
Solution Approach 1:
The patent segments the memory system into multiple separate memory blocks (first memory for parameters, second memory for input/output data) that can be accessed independently by the computer unit. This eliminates the need for a shared bus and allows parallel access to different data types, thereby increasing execution speed while managing complexity through modular organization.
Solution Approach 2:
The memory blocks are designed with multi-functional capabilities, where the first memory stores both neural network parameters and topology information, and the second memory handles both input data and generated output data. This universal design reduces the need for separate dedicated storage for each data type, balancing speed improvement with complexity control.
2Reliability
If more memory accesses are performed for neural network execution, then computation accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent implements preliminary action by pre-loading neural network parameters into the first memory and input data into the second memory before execution begins. The barrel shifter circuits are also pre-configured with shift amounts based on predetermined rules. This preliminary preparation reduces the need for repeated memory accesses during execution, thereby maintaining computation accuracy while reducing energy consumption.
Solution Approach 2:
The system employs self-service mechanisms where the barrel shifter circuits automatically perform data repositioning based on predetermined shift rules without requiring additional control signals or memory accesses. This self-service approach ensures accurate data retrieval while minimizing the energy cost associated with data handling operations.
3Use of energy by moving object
If barrel shifter circuits are used for data handling, then energy consumption is reduced, but device complexity increases
Solution Approach 1:
The patent extracts the data repositioning function from the main control unit and implements it through dedicated barrel shifter circuits with predetermined shift rules. By taking out this specific function and hardwiring it, the system reduces the energy consumption associated with dynamic control operations while managing complexity through functional specialization.
Solution Approach 2:
The barrel shifter circuits utilize parameter changes in the form of predetermined shift amounts that are configured based on the specific neural network topology and data requirements. This allows the same hardware structure to adapt to different computation scenarios, reducing energy consumption through optimized data positioning while avoiding the complexity of dynamically reconfigurable circuits.
4Speed
If separate memories are used for parameters and data, then execution speed is improved, but device complexity and dimensions increase
Solution Approach 1:
The patent merges multiple functions into the separate memory blocks: the first memory block handles both parameter storage and topology configuration, while the second memory block manages both input data and generated outputs. This merging of functions within segmented memory structures improves execution speed through parallel access while controlling overall circuit dimensions through functional consolidation.
Data Source
AI summary
An integrated circuit includes a computer unit configured to execute the neural network. Parameters of the neural network are stored in a first memory. Data supplied at the input of the neural network or generated by the neural network are stored in a second memory. A first barrel shifter circuit transmits data from the second memory to the computer unit. A second barrel shifter circuit delivers data generated during the execution of the neural network by the computer unit to the second memory. A control unit is configured to control the computer unit, the first and second barrel shifter circuits, and accesses to the first memory and to the second memory.