Neural Network Circuit With Dynamic Precision And Parallel Data Transmission
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Solution Overview
Problem
Existing neural network circuits face challenges in implementing a complete signal processing chain with multiple levels of precision, are often specialized for specific types of networks, and lack expandability and flexible dynamic behavior in coding weight vectors and inputs, leading to inefficiencies and increased power consumption.
Innovation Solution
An electronic circuit design that includes calculating blocks capable of implementing groups of neurons, a transformation block for data formatting, and communication channels for parallel data transmission, allowing for flexible precision and expandability through temporal and spatial coupling of processors and memory organization, along with a memory virtualization block for efficient weight sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional specialized processors are used for signal processing operations, then processing capability is improved, but system complexity and power consumption increase
Solution Approach 1:
The patent implements a universal neural processing architecture that can perform both conventional signal processing operations (convolutions, activations) and neural network computations using the same hardware blocks. The calculating blocks are designed to be reconfigurable, allowing them to adapt to different processing tasks through software configuration rather than requiring dedicated hardware for each operation type.
Solution Approach 2:
The patent merges signal processing functions and neural network processing functions into a single integrated architecture. The transformation blocks and calculating blocks serve dual purposes: they can process conventional signals and simultaneously implement neural network operations, eliminating the need for separate specialized processors and reducing overall system complexity.
2Productivity
If circuits are specialized for specific neural network types, then implementation efficiency is improved, but adaptability to different network types decreases
Solution Approach 1:
The patent employs dynamic reconfiguration capabilities where the calculating blocks can change their operational characteristics based on the specific neural network being implemented. The architecture allows runtime adjustment of parameters such as precision levels, network topology, and processing modes, enabling the same hardware to efficiently support multiple network types including RBF networks, Kohonen maps, and other architectures.
Solution Approach 2:
The patent creates a universal neural processing platform that can implement various neural network types through a common architecture. The transformation blocks and calculating blocks are designed with configurable parameters that allow them to adapt to different network requirements, maintaining high implementation efficiency across multiple network types without requiring specialized hardware for each.
3Reliability
If circuits are sized for worst-case scenario, then reliability is improved, but resource utilization efficiency decreases
Solution Approach 1:
The patent implements dynamic precision scaling where the calculating blocks can adjust their operational precision based on the current processing requirements. During learning phases, higher precision (16-bit) is used to ensure reliability, while during processing phases, lower precision (8-bit) suffices, improving resource utilization. This dynamic adaptation allows the system to maintain reliability when needed while maximizing efficiency during normal operation.
Solution Approach 2:
The patent changes operational parameters such as data precision and network size dynamically based on the processing phase and requirements. The architecture supports variable precision arithmetic and can configure the number of active neurons and connections according to the current task, allowing the system to operate reliably at full capacity when necessary while consuming fewer resources during less demanding operations.
4Ease of manufacture
If fixed precision coding is used, then implementation simplicity is improved, but flexibility in handling different precision requirements decreases
Solution Approach 1:
The patent implements dynamic precision control where the calculating blocks can switch between different precision levels (e.g., 8-bit, 16-bit) based on the operational phase and requirements. The transformation blocks include configurable precision settings that allow the system to use lower precision during processing for efficiency while switching to higher precision during learning for accuracy, all controlled through software configuration rather than hardware changes.
Solution Approach 2:
The patent enables parameter changes in data precision throughout the processing pipeline. The transformation blocks and calculating blocks support variable precision arithmetic, allowing the system to optimize the precision of weight vectors and input data according to the current task requirements. This maintains implementation simplicity through a unified architecture while providing flexibility in precision handling.
Data Source
AI summary
A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.