Artificial Neural Network Circuit Evaluation for Faster Verification

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Solution Overview

Problem

The increasing complexity of integrated circuits and the time and resource-intensive nature of circuit verification processes necessitate a more efficient method for circuit evaluation.

Innovation Solution

Utilizing a trained artificial neural network model to generate a target circuit graph, vector, and evaluation data, incorporating neural networks such as CNN, RNN, GAN, and transformer models to predict circuit performance metrics like gain, power, and delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional circuit verification methods are used, then measurement precision is maintained, but evaluation time increases significantly

Engineering Contradiction:
Improvecircuit evaluation accuracyVSAvoidcircuit evaluation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent creates a virtual copy of the circuit system through neural network models that replicate circuit behavior and characteristics. Instead of performing physical or detailed simulations on the actual circuit, the trained neural network model generates predicted performance data that mirrors real circuit responses, thereby maintaining accuracy while dramatically reducing evaluation time.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent performs preliminary training of neural network models using extensive circuit data and simulations before actual evaluation. This pre-training phase prepares the model to quickly predict circuit performance without requiring time-consuming simulations during the actual evaluation process, thus resolving the time-accuracy tradeoff.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive circuit tests are performed, then reliability is improved, but computing resources are excessively consumed

Engineering Contradiction:
Improvecircuit verification reliabilityVSAvoidcomputing resource consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces resource-intensive physical simulations with a virtual neural network model that has been trained to replicate circuit behavior. This virtual copy maintains the reliability needed for verification while consuming minimal computing resources during the evaluation phase, as the heavy computational work was performed during the one-time training process.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent transforms the circuit evaluation problem from requiring detailed simulation of all circuit parameters to using a trained neural network model that has already processed and stored relationships between input parameters and output performance metrics. This parameter transformation allows quick evaluation without re-computing complex simulations.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If detailed feature extraction is performed, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvedevice characteristic accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts only the most relevant circuit features and characteristics needed for performance prediction, rather than analyzing all possible circuit parameters. The neural network model is trained to identify and utilize key features that have the greatest impact on circuit performance, thereby maintaining manufacturing precision while reducing the effective complexity of the evaluation process.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250258985A1Method and apparatus for evaluating circuit using artificial neural network model
Publication Date: 2025.08.14 ALSEMY INC
  • US20250258985A1 patent drawing
  • US20250258985A1 patent drawing
  • US20250258985A1 patent drawing

AI summary

A circuit evaluation method performed by a computing device according to an embodiment of the present disclosure. The method includes generating a target circuit graph including a plurality of nodes and edges based on target circuit data, generating a target circuit vector based on the generated target circuit graph, and generating circuit evaluation data based on the target circuit vector.