Neural Network Processing Circuit With Stride-Aware Sparse Compression

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Deep learning inference calculations require extensive computational resources, limiting their effectiveness in mobile environments and high-speed processing environments due to high computational complexity.

Innovation Solution

A processing circuit utilizing a stride-aware compressed sparse row (SCSR) algorithm to compress output data of each layer in an artificial neural network by extracting non-zero values based on the stride of subsequent layers, reducing the need for searching valid input pairs and minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If deep learning inference calculations are performed using conventional methods, then calculation accuracy is maintained, but computational complexity increases and processing speed decreases

Engineering Contradiction:
Improveprocessing speedVSAvoidcomputational complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts only the non-zero values from the output data of each layer using a stride-aware compressed sparse row algorithm. By removing zero values that do not contribute to the final result, the data volume is significantly reduced, enabling faster processing and reduced computational complexity in subsequent layers while maintaining calculation accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs compression of output data before it is passed to subsequent layers. By pre-compressing the data using the stride-aware algorithm that leverages knowledge of the next layer's stride, the system prepares optimized input data in advance, reducing the computational burden on subsequent layers and improving overall processing speed.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If conventional compression methods are used, then data volume is reduced, but additional circuits and storage are required for searching valid input pairs

Engineering Contradiction:
Improvedata volumeVSAvoidcircuit complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The compression circuit performs compression operations autonomously using the stride-aware compressed sparse row algorithm without requiring external assistance from separate searching circuits or additional storage units. The circuit leverages the stride information of the next layer to directly identify and compress non-zero values, making the system self-sufficient and eliminating the need for complex additional hardware.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The compression circuit is designed to handle multiple functions within a single unit: it identifies non-zero values, compresses the data, and prepares it for the next layer all in one operation. This multi-functional approach eliminates the need for separate circuits for searching valid input pairs and storing compressed data, reducing overall device complexity while maintaining data volume reduction benefits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250226840A1Processing circuit for artificial neural network, method of operating the processing circuit, and system including the same
Publication Date: 2025.07.10 SAMSUNG ELECTRONICS CO LTD
  • US20250226840A1 patent drawing
  • US20250226840A1 patent drawing
  • US20250226840A1 patent drawing

AI summary

Provided are a processing device configured to compress the output data of a first layer into second compressed input data by extracting non-zero values from the output data of the first layer by using a stride-aware compressed sparse row (SCSR) algorithm based on stride of a second layer in the artificial neural network and output the second compressed input data as input data of the second layer.