Neural Core Clock Gating Based on Data Flow Activity
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Solution Overview
Problem
The challenge of high power consumption in neural processing units (NPUs) due to parallel operation of multiple compute units in artificial intelligence systems is not effectively addressed by existing technologies.
Innovation Solution
Implementing a clock gating method for neural processors based on a data flow architecture, utilizing a clock controller to selectively gate clock signals to compute units based on their operation states, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple compute units are operated in parallel to increase computation efficiency, then processing speed is improved, but power consumption increases in proportion to the number of compute units
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signal to compute units is selectively enabled or disabled based on real-time operation states. The operation controller dynamically adjusts clock signal distribution to active compute units only, transforming the static power consumption model into a dynamic one that adapts to workload requirements, thereby reducing power consumption while maintaining computational efficiency.
Solution Approach 2:
The patent changes the operational parameter of compute units by controlling the presence or absence of clock signals. When a compute unit completes its operation or is in an idle state, the clock signal is gated off, effectively changing its operational state from active to inactive. This parameter change allows the system to maintain high computation efficiency when needed while minimizing power consumption during idle periods.
2Productivity
If clock signals are continuously provided to all compute units, then computation efficiency is maintained, but power consumption increases
Solution Approach 1:
The patent extracts the clock signal from inactive compute units by implementing clock gating control. The operation controller identifies which compute units are actively processing data and which are idle, then selectively removes the clock signal from inactive units. This extraction principle allows the system to maintain computation efficiency for active units while eliminating unnecessary energy loss to inactive units.
Solution Approach 2:
The operation controller monitors the operation states of compute units and autonomously decides when to gate or ungat clock signals based on data flow architecture requirements. This self-service mechanism allows the system to automatically optimize power consumption without external intervention, maintaining computation efficiency while reducing energy loss through intelligent, autonomous clock signal management.
3Use of energy by moving object
If clock gating is implemented to reduce power consumption, then energy efficiency is improved, but system complexity increases due to additional control mechanisms
Solution Approach 1:
The operation controller serves multiple functions: it manages data flow architecture, monitors operation states of compute units, generates operation state signals, and controls clock gating decisions. By consolidating these diverse functions into a single multi-functional controller, the patent reduces overall system complexity compared to having separate dedicated circuits for each function, while still achieving effective power consumption reduction through clock gating.
Data Source
AI summary
Provided are a neural processor, a neural processing device, and a clock gating method thereof, which perform clock gating for a plurality of compute units based on a data flow architecture, in which the neural processor includes at least one neural core that processes at least one task, and a clock controller that selectively gates, according to a data flow architecture of the at least one task, a clock signal provided to the at least one neural core.