Neural Core Config ID Assignment for Scalable Processor Arrays
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Solution Overview
Problem
Increasing the number of cores in neural processing units leads to increased design complexity and reduced scalability, necessitating additional ports for core IDs, which complicates miniaturization and computation efficiency.
Innovation Solution
A neural processor design that assigns config IDs to cores via a config line, allowing for reconfiguration of data paths and reducing power consumption by managing core arrays through an ID config manager and task manager.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cores is increased to maximize computation efficiency, then computation efficiency is improved, but design complexity increases and scalability is reduced
Solution Approach 1:
The patent merges the core ID indication function into the existing data path structure by using data lines to carry both data and core identification information. Instead of adding separate ID ports for each core, the system combines multiple functions into the existing data transmission infrastructure, thereby reducing overall design complexity while maintaining the ability to scale the number of cores.
Solution Approach 2:
The data lines in the processor are designed to serve multiple functions: they transmit both computational data and core identification information. This multi-functionality eliminates the need for dedicated ID ports, allowing the system to scale to more cores without proportionally increasing the number of required ports and connections, thus improving scalability while maintaining computation efficiency.
2Productivity
If the number of cores is increased, then computation efficiency is improved, but scalability is reduced due to increased number of ports required
Solution Approach 1:
The patent combines the core ID indication function with the existing data transmission paths. By merging these functions, the system avoids the need to add separate ID ports for each additional core, thereby maintaining scalability while supporting an increased number of cores for improved computation efficiency.
Solution Approach 2:
The data lines are designed to universally handle both data transmission and core ID indication. This multi-functional design allows the processor to scale to more cores without requiring a proportional increase in the number of ports, thus preserving scalability while enabling higher computation efficiency through increased core count.
3Measurement precision
If separate ports are added for each core ID, then core identification capability is improved, but device complexity and miniaturization difficulty increase
Solution Approach 1:
The patent merges the core ID indication function into the existing data path infrastructure. By combining these functions, the system maintains accurate core identification capability while avoiding the addition of separate ID ports, thereby reducing design complexity and facilitating chip miniaturization.
4Measurement precision
If separate ports are added for each core ID, then core identification capability is improved, but miniaturization becomes more difficult
Solution Approach 1:
The patent combines the core ID indication function with the existing data transmission paths. This merging eliminates the need for additional separate ID ports, thereby reducing the overall chip area required and making miniaturization more feasible while maintaining accurate core identification capability.
Data Source
AI summary
A neural processor and method for assigning config ID for neural core included in the same are provided. The neural processor includes a core array comprising a first neural core, a second neural core, a first data line connecting the first neural core and the second neural core in series, and a config line connecting the first neural core and the second neural core in series, an ID config manager configured to assign a first config ID to the first neural core and a second config ID to the second neural core via the config line, and a memory configured to input and output data to and from the core array via the first data line.