Neural Core On-Chip Memory for Lower-Power Data Processing
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Solution Overview
Problem
Existing neural processing units face challenges in efficiently processing large amounts of data for deep-learning tasks due to increased power consumption and calculation complexity as the number of neural cores increases, necessitating improved energy efficiency and data processing efficiency.
Innovation Solution
Implementing a neural core with an on-chip memory that performs one-dimensional calculations, utilizing a memory load/store unit, local memory banks, and a scheduler to manage data storage and loading, thereby reducing the need for two-dimensional convolution calculations and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of neural cores is increased to maximize calculation amount, then calculation capability is improved, but power consumption and calculation complexity increase
Solution Approach 1:
The patent segments the calculation tasks into two-dimensional convolution calculations handled by neural cores and one-dimensional calculations handled by on-chip memory. This division allows each component to specialize in specific calculation types, reducing overall system complexity and power consumption while maintaining high calculation capability through parallel processing
Solution Approach 2:
The on-chip memory acts as an intermediary component that handles one-dimensional calculations between neural cores and external memory. This intermediary structure reduces the computational burden on neural cores and enables more efficient data processing without requiring proportional increases in neural core数量
2Measurement precision
If two-dimensional convolution calculations are performed in processing unit, then calculation accuracy is improved, but processing time and power consumption increase
Solution Approach 1:
The patent segments calculation operations by performing two-dimensional convolution in the processing unit for high accuracy requirements, while delegating one-dimensional calculations to the on-chip memory. This segmentation allows the system to maintain calculation accuracy where needed while reducing processing time for simpler operations
Solution Approach 2:
The patent transitions from performing all calculations in the processing unit to distributing calculations across different dimensional levels - two-dimensional convolutions in the processing unit and one-dimensional operations in memory. This dimensional division optimizes both accuracy and processing time by matching calculation complexity with appropriate hardware resources
3Adaptability or versatility
If one-dimensional calculations are performed in processing unit, then calculation flexibility is improved, but device complexity increases
Solution Approach 1:
The on-chip memory is designed with multi-functionality, serving both as storage and as a processing unit for one-dimensional calculations. This universal design eliminates the need for separate dedicated hardware for one-dimensional operations, reducing device complexity while maintaining calculation flexibility
Solution Approach 2:
The on-chip memory performs one-dimensional calculations autonomously without requiring extensive control from the processing unit. This self-service capability reduces the complexity of the overall system by allowing the memory subsystem to handle certain calculation tasks independently
Data Source
AI summary
A neural core, a neural processor, and a data processing method thereof are provided. The neural core includes a processing unit configured to generate output activation by performing calculation of input activation and a weight, a memory load/store unit configured to generate a memory calculation request requesting one-dimensional calculation of summing the output activation and target data, and a memory configured to receive the output activation and the memory calculation request, import the target data from a memory address in response to the memory calculation request, generate output data by performing the one-dimensional calculation of the target data and the output activation, and store the generated output data in the memory address.