Reconfigurable Neural Core Partitioning for Layer-Specific Parallelism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing parallel computational architectures for neural networks face limitations in utilizing available parallelism due to fixed sizes and configurations, which hinder efficient execution of neural network computations, especially as layer dimensions vary significantly within a network.
Innovation Solution
A reconfigurable parallel computational architecture that partitions neural cores and vector units based on layer dimensions, allowing for dynamic allocation and efficient mapping of data and operations across cores and vector units, enabling both core-level and vector-level parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed-size parallel computational architecture is used, then device simplicity is maintained, but adaptability to varying layer dimensions deteriorates
Solution Approach 1:
The parallel computational architecture implements dynamic reconfiguration of core groups and vector units based on the dimensional characteristics of each neural network layer. The system can adaptively adjust the number of active cores and vector unit configurations to match the computational requirements of different layer sizes, transforming a static architecture into a dynamic one that responds to varying workloads.
Solution Approach 2:
The computational architecture is divided into multiple independent core groups, where each group can be independently configured and activated. This segmentation allows the system to selectively enable only the necessary number of core groups for each layer computation, providing flexibility in adapting to different layer dimensions while maintaining manageable system complexity through modular organization.
2Productivity
If fixed configuration of vector units is used, then device complexity is reduced, but productivity varies significantly with layer dimensions
Solution Approach 1:
The vector units are configured dynamically based on the dimensional characteristics of each neural network layer. The system adjusts the number of vector units and their operational parameters to match the computational density requirements of different layers, ensuring optimal productivity for each layer while maintaining a relatively simple base configuration that can be adaptively scaled.
3Productivity
If cores are not partitioned based on layer dimensions, then ease of operation is maintained, but core utilization efficiency deteriorates
Solution Approach 1:
The total set of computational cores is segmented into multiple core groups that can be independently controlled and configured. This segmentation enables the system to partition and activate only the necessary number of core groups for each layer computation, improving core utilization efficiency while maintaining ease of operation through automated or semi-automated partitioning strategies that reduce manual configuration complexity.
4Loss of time
If vector units are not adaptively configured, then device complexity is minimized, but loss of time occurs due to underutilization
Solution Approach 1:
The vector unit configuration is made dynamic and adaptive to the dimensional characteristics of each neural network layer. The system automatically reconfigures the number and arrangement of vector units based on the computational requirements of the current layer, minimizing processing time by ensuring optimal utilization of vector computing resources while managing reconfiguration complexity through systematic adaptation strategies.
Data Source
AI summary
Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.