Neural Core Sync ID Logic for Parallel Load-Store Execution

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Solution Overview

Problem

Existing neural processing units (NPUs) face significant waiting times due to the sequential nature of synchronization signal transmission, which limits the efficiency of deep-learning tasks.

Innovation Solution

A neural processing device that groups load and store instructions and executes them in parallel, utilizing a sync ID logic to generate synchronization signals for each group, allowing simultaneous execution without waiting times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If synchronization signals are transmitted sequentially, then the transmission order is maintained, but waiting time increases

Engineering Contradiction:

Improvesynchronization waiting timeVSAvoidinstruction execution efficiency

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The patent segments instructions into groups with unique sync IDs, allowing parallel transmission of synchronization signals for different groups while maintaining order within each group. This segmentation enables multiple instructions to be processed simultaneously without complete sequential dependency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent assigns sync IDs to instruction groups in advance before execution, enabling the synchronization system to prepare and transmit signals for multiple groups simultaneously. This preliminary assignment eliminates the need for sequential signal generation and reduces waiting time.

Inventive Principle:

Principle #10Preliminary action

2Speed

If instructions are executed in parallel, then execution speed increases, but synchronization control complexity increases

Engineering Contradiction:

Improveinstruction execution speedVSAvoidsynchronization signal management

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent introduces sync ID as an intermediary parameter that mediates between parallel instruction execution and synchronization control. Each instruction group is tagged with a sync ID, allowing the system to manage complex parallel operations through simple ID-based routing and matching of synchronization signals.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The sync ID mechanism serves multiple functions simultaneously: it identifies instruction groups, controls synchronization timing, manages signal routing, and maintains execution order. This multi-functionality reduces the need for separate control mechanisms for each aspect of parallel execution management.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12579069B2Neural processing device

Publication Date: 2026.03.17 REBELLIONS INC

AI summary

A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.