Neural Network Data Encoding for Skipping Invalid Bit Operations
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Solution Overview
Problem
Current neural network training methods face inefficiencies due to the need for processing non-consecutive invalid bits, which consume resources and reduce learning performance.
Innovation Solution
A method and apparatus that compress consecutive invalid bits into a single bit and generate a validity determination sequence, allowing the neural network to omit operations on non-consecutive invalid bits, thereby improving processing efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional neural network training methods process all bits including non-consecutive invalid bits, then complete data processing is achieved, but processing efficiency and power consumption are degraded
Solution Approach 1:
The patent extracts and removes invalid bits (zeros) from the data sequence before inputting to the neural network. The encoding circuit identifies consecutive invalid bits and compresses them, extracting only the valid information bits for processing. This eliminates unnecessary computations on invalid data, directly improving processing efficiency and reducing power consumption.
Solution Approach 2:
The patent discards invalid bits during the encoding phase by compressing consecutive zeros into a compact representation. The decoding circuit later recovers the original data structure by expanding the compressed representation back to the full bit sequence, but only after the neural network has processed the essential valid information. This discard-and-recover approach eliminates wasteful processing while preserving data integrity.
2Loss of information
If all bits in the data sequence are transmitted to the neural network circuit, then data completeness is maintained, but processing time and computational resources are wasted on invalid bits
Solution Approach 1:
The patent performs preliminary compression of the data sequence in the encoding circuit before the neural network processing. Consecutive invalid bits are compressed into a compact form that preserves the ability to reconstruct the original data if needed, while significantly reducing the number of bits that require neural network processing. This preliminary action maintains data completeness while minimizing processing time.
Solution Approach 2:
The patent introduces an intermediary encoding/decoding circuit system between the data source and the neural network. The encoding circuit acts as a mediator that transforms the original data into a compressed representation, and the decoding circuit acts as another mediator that reconstructs the data after neural network processing. This intermediary system ensures data completeness is maintained while reducing processing time.
3Productivity
If consecutive invalid bits are compressed into a single bit, then data transmission efficiency is improved, but the device complexity increases due to encoding and decoding circuits
Solution Approach 1:
The patent segments the data processing function into three distinct modules: an encoding circuit that compresses consecutive invalid bits, a neural network circuit that processes only valid bits, and a decoding circuit that reconstructs the original data. This segmentation allows each module to be optimized independently, improving overall data transmission efficiency while managing device complexity through functional decomposition.
Solution Approach 2:
The encoding and decoding circuits serve multiple functions: they compress data to improve transmission efficiency, they maintain data completeness for potential reconstruction, and they interface with the neural network circuit. This multi-functionality justifies the added device complexity by providing multiple benefits from a single integrated system.
Data Source
AI summary
A neural network deep learning data control apparatus includes: a memory; an encoding circuit configured to receive a data sequence, generate a compressed data sequence in which consecutive invalid bits in a bit string of the data sequence are compressed into a single bit of the compressed data sequence, generate a validity determination sequence indicating a valid bit and an invalid bit in a bit string of the compressed data sequence, and write the compressed data sequence and the validity determination sequence to the memory; and a decoding circuit configured to read the compressed data sequence and the validity determination sequence from the memory, and determine a bit in the bit string of the compressed data sequence set for transmission to a neural network circuit, based on the validity determination sequence, such that the neural network circuit omits an operation with respect to non-consecutive invalid bits.