Virtualized Data Iterators for Neural Network Memory Bottlenecks

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Solution Overview

Problem

Existing neural networks and deep neural networks face performance issues due to inefficient data processing, including avoidable processing time and memory management problems, which lead to increased latency and computational overhead.

Innovation Solution

The implementation of virtualized hardware iterators in neural network environments allows for optimized data processing by specifying dimensions and configuring iterations, enabling parallel processing and improved memory management through the use of iterator controllers, load/store controllers, and DMA operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional data processing methods are used in neural networks, then the system structure is simple, but the processing time increases and latency increases

Engineering Contradiction:
Improvedata processing speedVSAvoidprocessing time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent segments the data processing task by introducing iterator controllers that divide large data sets into smaller chunks or batches. These iterators traverse the data in manageable portions, allowing parallel processing and reducing the time each processing unit waits for data, thereby improving overall processing speed while maintaining system simplicity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-configuring iterator controllers with traversal parameters, data dimensions, and processing instructions before actual data processing begins. This pre-preparation enables the iterators to immediately begin efficient data traversal when processing starts, reducing initial latency and improving processing speed without complicating the core neural network architecture.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If traditional data processing methods are used in neural networks, then the implementation is simple, but memory management efficiency decreases

Engineering Contradiction:
Improvememory management efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces iterator controllers as intermediary components between the data source and the neural network processing units. These iterators act as mediators that manage data flow, control memory access patterns, and coordinate between different processing elements. This intermediary layer improves memory management efficiency by optimizing data retrieval and transmission without requiring fundamental changes to the neural network's core architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If traditional data processing methods are used in neural networks, then the computational operations are straightforward, but computational overhead increases

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidcomputational overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent ensures continuity of useful action by implementing iterator controllers that continuously traverse and supply data to processing units without interruption or idle time. The iterators are designed to maintain steady data flow, eliminating gaps between computational operations. This continuous data supply reduces computational overhead by ensuring processing units remain constantly productive, improving overall computational efficiency.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11030131B2Data processing performance enhancement for neural networks using a virtualized data iterator
Publication Date: 2021.06.08 MICROSOFT TECHNOLOGY LICENSING LLC
  • US11030131B2 patent drawing
  • US11030131B2 patent drawing
  • US11030131B2 patent drawing

AI summary

The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. Using virtualized hardware iterators, data for processing by the NN/DNN can be traversed and configured to optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, an iterator controller can generate instructions for execution by the NN/DNN representative of one more desired iterator operation types and to perform one or more iterator operations. Data can be iterated according to a selected iterator operation and communicated to one or more neuron processors of the NN/DD for processing and output to a destination memory. The iterator operations can be applied to various volumes of data (e.g., blobs) in parallel or multiple slices of the same volume.