Neural Decoding of Concatenated Codes for NAND Flash Reliability

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Solution Overview

Problem

Flash memory devices, such as NAND flash memory, experience errors due to noise and interference during programming and read operations, which existing error correction codes struggle to address effectively, especially under high stress conditions.

Innovation Solution

A memory system utilizing a deep neural network (DNN) decoder that performs soft decoding by receiving log-likelihood ratios, determining extrinsic estimation functions, and updating LLR values through iterative processes to correct errors, improving error correction capability and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional error correction codes are used for NAND flash memory, then programming speed can be maintained, but error correction capability deteriorates under high stress conditions

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces traditional algebraic decoding algorithms with a neural network-based system that uses soft computing to decode error correction codes. The neural network processes log-likelihood ratios and syndrome information to directly output corrected codewords, eliminating the need for complex algebraic algorithms like Berlekamp-Massey or Euclidean algorithms, thereby reducing decoding complexity while maintaining or improving error correction capability under stress conditions

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational parameters of error correction by using soft information (log-likelihood ratios) instead of hard decisions, and by adjusting the neural network's internal parameters (weights and biases) through training on synthetic data that models various stress conditions. This allows the system to adapt to changing channel conditions and maintain high reliability without increasing decoding complexity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If strong error correction codes are used, then error correction capability improves, but programming speed deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprogramming speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary training of the neural network offline using synthetic data that models various stress conditions and error patterns. This pre-computes the optimal decoding behavior, so that during actual programming and decoding operations, the neural network can quickly process received signals without requiring complex real-time computations, thereby maintaining high programming speed while achieving strong error correction capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses synthetic training data that copies and models various stress conditions and error patterns that might occur in real NAND flash memory operations. By training on these copied scenarios, the neural network learns to handle real stress conditions efficiently, achieving strong error correction without the overhead of complex real-time processing that would slow down programming operations

Inventive Principle:
Principle #26Copying

Data Source

PatentUS12176924B2Deep neural network implementation for concatenated codes
Publication Date: 2024.12.24 KIOXIA CORP
  • US12176924B2 patent drawing
  • US12176924B2 patent drawing
  • US12176924B2 patent drawing

AI summary

Systems, methods, non-transitory computer-readable media configured to perform operations associated with a storage medium. One system includes the storage medium and an encoding/decoding (ED) system, the ED system being configured to receive a set of input log-likelihood ratios (LLRs) of a component of the plurality of components, determine an extrinsic estimation function based on a set of features of the set of input LLRs, analyze the extrinsic estimation function to obtain a plurality of extrinsic LLR values, map the plurality of extrinsic LLR values to an input LLR of the set of input LLRs, and output, for each component, a plurality of updated LLR values based on the mapping.