Neural Network Dot Product Accelerator With On-Chip Vector Caching
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Solution Overview
Problem
Current methods for calculating dot products in multilayer neural networks, such as using general-purpose processors or GPUs, face performance bottlenecks due to low processing efficiency and high power consumption, especially when dealing with vectors of large numbers of elements.
Innovation Solution
A neural network acceleration processor is introduced, comprising a controller unit, direct memory access unit, and caching unit, which retrieves and stores vectors and performs dot product calculations efficiently by using a computation module with multipliers and an adder to sum multiplication results directly, optimizing performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a general-purpose processor is used to calculate dot product, then the system is simple and versatile, but processing performance is low and cannot meet requirements for large vectors
Solution Approach 1:
The processor is divided into specialized functional units: vector operation units for parallel dot product calculations, caching units for vector data storage, and control units for instruction management. This segmentation enables high-performance vector processing while maintaining modular architecture.
Solution Approach 2:
Caching units are introduced as intermediaries between off-chip memory and computation units. These caches store vector elements locally, reducing repeated off-chip data movements and alleviating the bandwidth bottleneck that limits GPU performance.
2Productivity
If GPU is used to calculate dot product, then parallel processing capability is improved, but off-chip bandwidth becomes bottleneck causing huge power consumption
Solution Approach 1:
Vector elements are pre-loaded into on-chip caching units before computation begins. This preliminary action ensures that data is already available in fast on-chip memory when computation starts, eliminating the need for repeated off-chip data movements that consume excessive power.
Solution Approach 2:
On-chip caching units serve as intermediaries between off-chip memory and computation units. By storing vector elements locally, these caches reduce the frequency and volume of off-chip memory accesses, thereby reducing power consumption associated with off-chip bandwidth usage.
3Productivity
If GPU with small on-chip caching is used, then device complexity is reduced, but data must be repeatedly moved from off-chip causing performance bottleneck
Solution Approach 1:
Vector data is pre-loaded into on-chip caching units before the dot product computation begins. This preliminary data loading ensures that all necessary vector elements are available in fast on-chip memory throughout the computation, eliminating repeated off-chip data movements and associated time delays.
Solution Approach 2:
On-chip caching units act as intermediaries that buffer vector data between off-chip memory and computation units. This intermediary storage eliminates the need for repeated slow off-chip memory accesses during computation, significantly reducing data movement time and improving overall calculation speed.
Data Source
AI summary
Aspects for generating a dot product for two vectors in neural network are described herein. The aspects may include a controller unit configured to receive a vector load instruction that includes a first address of a first vector and a length of the first vector. The aspects may further include a direct memory access unit configured to retrieve the first vector from a storage device based on the first address of the first vector. Further still, the aspects may include a caching unit configured to store the first vector.