Neural Network Error Identification via External Memory Controller

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Solution Overview

Problem

Existing machine learning systems using artificial neural networks face challenges in accurately identifying and correcting errors within the calculation hardware, which can lead to unreliable neural output values due to hardware malfunctions.

Innovation Solution

A method and device that utilize a layer description and network description for an artificial neural network, enabling communication between calculation hardware and a memory controller using a predefined data format to perform error identification and correction outside the calculation hardware by determining test sums and reference values, allowing for reliable operation and external usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error identification is performed inside the calculation hardware, then the error detection capability is improved, but the device complexity and reliability requirements of the calculation hardware increase

Engineering Contradiction:
Improveerror detection capabilityVSAvoidcalculation hardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error identification functionality is extracted from the calculation hardware and implemented in the memory controller instead. The memory controller performs error detection by comparing test sums with reference values, while the calculation hardware focuses solely on neural network computations. This separation reduces the complexity of the calculation hardware while maintaining error detection capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory controller acts as an intermediary between the calculation hardware and the memory system, handling error identification tasks. It receives neural network data from the calculation hardware, performs error detection by calculating and comparing sums, and manages data transfer. This intermediary approach allows error detection without adding complexity to the calculation hardware.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a standardized data format for communication between calculation hardware and memory controller is implemented, then the adaptability and ease of operation are improved, but the device complexity increases due to protocol definition and implementation

Engineering Contradiction:
Improvehardware compatibilityVSAvoidcommunication protocol complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A universal data format is defined for communication between the memory controller and calculation hardware, enabling the memory controller to work with arbitrary calculation hardware that supports this format. The standardized protocol includes structured messages for data transfer, error identification, and control operations, making the system adaptable to different hardware implementations while maintaining consistent communication rules.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If error identification is performed outside the calculation hardware in the memory controller, then the calculation hardware reliability requirements are reduced, but the memory controller complexity increases

Engineering Contradiction:
Improvecalculation hardware reliabilityVSAvoidmemory controller complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory controller performs self-service by implementing error identification functionality within itself. It calculates test sums from received data, compares them with reference values, and identifies errors without requiring additional external error detection hardware. This self-contained approach reduces reliance on ultra-reliable calculation hardware while keeping the added complexity localized to the memory controller.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12561554B2Error identification for an artificial neural network
Publication Date: 2026.02.24 ROBERT BOSCH GMBH
  • US12561554B2 patent drawing
  • US12561554B2 patent drawing

AI summary

A device and method for machine learning using an artificial neural network. For a calculation hardware for the artificial neural network, a layer description is provided, which defines at least one part of a layer of the artificial neural network, the layer description defining a tensor for input values of at least one part of this layer, a tensor for weights of at least one part of this layer, and a tensor for output values of at least one part of this layer, in particular of its starting address. A message that includes a start address of the tensor for the input values, or of the tensor for the weighs, or of the tensor for the output values is sent by the calculation hardware for transfer of the input values, or the weights, or the output values, is sent by the calculation hardware.