Neural Model Predicting IP Block PPA from HDL

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Solution Overview

Problem

Current methods for evaluating the performance, power, and area (PPA) of intellectual property (IP) blocks in integrated circuit design are impractical during early architectural design stages, as they require synthesis into a gate-level netlist, a process that can take hours to days for large IPs.

Innovation Solution

A system and method using a machine learning model to predict the physical behavior of IP blocks directly from their hardware description language (HDL) representation, allowing for the estimation of characteristics such as delays, area, and power, thereby shortening the IP development cycle and providing more optimal solutions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional synthesis into gate-level netlist is used to evaluate PPA, then measurement precision is improved, but loss of time worsens significantly

Engineering Contradiction:
ImprovePPA evaluation accuracyVSAvoidsynthesis time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent creates a neural network model that learns from actual synthesis results to predict PPA characteristics. Instead of performing full synthesis during early design stages, the system uses a trained neural network model to generate accurate predictions by copying the essential evaluation capability from synthesized data, thereby avoiding the time-consuming synthesis process while maintaining measurement precision

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent performs synthesis and training in advance to build a pre-trained neural network model. The model is trained offline using synthesized data from representative IP blocks, so that during actual design evaluation, the pre-trained model can provide rapid PPA predictions without requiring real-time synthesis, thus resolving the time-accuracy tradeoff

Inventive Principle:
Principle #10Preliminary action

2Reliability

If synthesis into gate-level netlist is performed, then reliability of PPA evaluation is improved, but productivity worsens due to long evaluation time

Engineering Contradiction:
ImprovePPA evaluation reliabilityVSAvoiddesign iteration speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The neural network model captures the reliable PPA evaluation capability from actual synthesis results and copies this evaluation function into a predictive model. The model is trained on synthesized data to learn the relationship between HDL parameters and PPA characteristics, enabling reliable predictions without repeated synthesis operations, thus improving productivity while maintaining evaluation reliability

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent replaces the mechanical synthesis process with a neural network-based prediction system. Instead of repeatedly performing resource-intensive synthesis operations to evaluate different design scenarios, the system uses the trained neural network to rapidly predict PPA outcomes, substituting the mechanical synthesis workflow with an intelligent prediction mechanism that preserves reliability while enhancing productivity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250173490A1System and method for training a neural learning model for predicting performance, power and area behavior of IP components in integrated circuit design
Publication Date: 2025.05.29 ARTERIS INC
  • US20250173490A1 patent drawing
  • US20250173490A1 patent drawing
  • US20250173490A1 patent drawing

AI summary

A system, and corresponding method, is described for training a neural learning model and using the neural learning model to predict the physical behavior of IP from an HDL representation of the IP. The generated data is used for training and testing the neural learning model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters. The method compresses timing arcs. The system uses the trained neural learning model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.