Neural Network Matrix Multiplication via Bitwise Shift and Addition
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Solution Overview
Problem
In multilayer neural networks, particularly in convolution neural networks, the large number of convolution operations significantly reduces processing speed, impairing practical applications due to high computational resource consumption by multiplication operations.
Innovation Solution
The implementation of a neural network operation device that replaces multiplication processors with adders and bitwise shifters, using a matrix element storage module to store bits in sequence and a numeric operation module to perform exclusive disjunction and summation operations, thereby reducing computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiplication operations are used in convolution neural networks, then computational accuracy is maintained, but processing speed decreases and power consumption increases
Solution Approach 1:
The patent changes the computational parameters by replacing multiplication operations with addition operations combined with bitwise shift operations. This parameter change transforms the mathematical operation from O(1) multiplication to O(log n) addition-shift combinations, reducing computational complexity and power consumption while maintaining numerical accuracy through proper handling of binary representations
Solution Approach 2:
The patent substitutes the mechanical multiplication operation with a combination of addition and bitwise shift operations. This substitution replaces complex multiplication circuitry with simpler adder circuits and shift registers, reducing hardware complexity, processing time, and energy consumption while achieving the same computational result
2Measurement precision
If multiplication processors are used, then computational precision is maintained, but device complexity increases
Solution Approach 1:
The patent substitutes complex multiplication processor architecture with simpler addition circuits and bitwise shift mechanisms. This substitution maintains computational precision by using binary representation properties where shifts correspond to power-of-2 multiplications, and additions handle the remaining cases, achieving the same result with reduced hardware complexity
Solution Approach 2:
The patent segments the multiplication operation into multiple simpler operations: bitwise decomposition of operands, conditional addition based on bit patterns, and shift operations for positional weighting. This segmentation breaks down the complex multiplication task into manageable addition and shift steps, reducing device complexity while preserving precision
3Reliability
If large number of convolution operations are performed, then neural network accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent substitutes multiplication operations with addition and bitwise shift operations throughout the convolution process. This substitution maintains the accuracy of neural network computations while significantly speeding up processing, as addition and shift operations can be executed faster and in parallel with simpler circuitry compared to multiplication operations
Data Source
AI summary
Aspects of a neural network operation device are described herein. The aspects may include a matrix element storage module configured to receive a first matrix that includes one or more first values, each of the first values being represented in a sequence that includes one or more bits. The matrix element storage module may be further configured to respectively store the one or more bits in one or more storage spaces in accordance with positions of the bits in the sequence. The aspects may further include a numeric operation module configured to calculate an intermediate result for each storage space based on one or more second values in a second matrix and an accumulation module configured to sum the intermediate results to generate an output value.