Neural Network Memory Array for High-Precision Edge Inference
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Solution Overview
Problem
Existing neural network devices face challenges in performing precise calculations due to size limitations when implemented as edge computing devices, particularly with high-resolution memory cells and digital-to-analog converters occupying large areas, leading to increased costs and device size.
Innovation Solution
A neural network device incorporating a digital-to-analog converter, a cell array with memory cells, and an analog-to-digital converter, along with a processor, that allows for precise bit operations by converting digital inputs to analog signals, performing operations within the cell array, and converting back to digital outputs, optimizing bit resolution and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution memory cells and digital-to-analog converters are used, then calculation precision is improved, but device size increases
Solution Approach 1:
The patent segments the bit operations into multiple parallel operations across multiple bit lines. Each bit line performs operations on specific bit positions simultaneously, allowing high-precision calculations to be distributed across many low-resolution components rather than requiring a single high-resolution component.
Solution Approach 2:
The patent transitions from a single high-resolution analog computation dimension to a multi-dimensional approach using parallel bit lines and word lines. By organizing memory cells in a grid structure with multiple bit lines and word lines, the system achieves high precision through the combination of multiple lower-resolution operations across different dimensions.
2Measurement precision
If high-resolution memory cells and digital-to-analog converters are used, then calculation precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent divides the computation into segments across multiple bit lines, where each bit line uses simpler, lower-cost low-resolution memory cells and converters. This segmentation allows the system to achieve high precision through parallel low-resolution operations rather than requiring expensive high-resolution components.
Solution Approach 2:
The patent employs inexpensive low-resolution memory cells and converters that can be mass-produced, replacing costly high-resolution components. The low-resolution components are used in parallel across multiple bit lines, and their simplicity makes them easier and cheaper to manufacture at scale.
3Speed
If computing is performed in memory, then calculation speed is improved, but device size for edge computing increases
Solution Approach 1:
The patent segments the in-memory computation into parallel operations across multiple bit lines and word lines. This segmentation allows the edge computing device to perform fast in-memory calculations using a distributed array of simple memory cells, achieving high speed without requiring a single large high-resolution memory structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise calculations with reduced device size and cost by utilizing low-resolution components effectively, enhancing power efficiency and reducing heat generation through on-chip memory operations.
Implementation Method 1
a digital-to-analog converter configured to convert a digital input to an analog input of either voltage or current
Implementation Method 2
configured to perform an operation on the analog input that is input through the word lines and output an analog output of any one of current and voltage, through the bit lines
Implementation Method 3
an analog-to-digital converter configured to convert the analog output into a digital output
Data Source
AI summary
A neural network device includes: a digital-to-analog converter configured to convert a digital input to an analog input of either voltage or current; a cell array including a plurality of memory cells arranged in a plurality of bit lines and a plurality of word lines and configured to store a weight of a neural network, and configured to perform an operation on the analog input that is input through the word lines and output an analog output of any one of current and voltage, through the bit lines; an analog-to-digital converter configured to convert the analog output into a digital output; and at least one processor electrically connected to the digital-to-analog converter and the analog-to-digital converter and configured to control the digital input and the digital output.