Analog Neural Memory Readout Using Bit-Shifted Digital Output
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Solution Overview
Problem
Existing technologies face challenges in implementing efficient programming, verifying, and reading systems for non-volatile memory cells in analog neuromorphic memory systems, particularly in vector-by-matrix multiplication (VMM) arrays, which are essential for enhancing neural network performance.
Innovation Solution
The solution involves a system for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array, utilizing a combination of CMOS technology and non-volatile memory arrays, where input bits are processed and output bits are digitized, shifted, and added to yield an output indicating the stored value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If non-volatile memory arrays are used for analog neuromorphic computing, then energy efficiency is improved, but programming precision and verification capability deteriorate
Solution Approach 1:
The patent introduces an intermediary verification system that reads back programmed values from non-volatile memory cells and compares them against target values. This mediator component enables precise verification of programming accuracy without requiring the memory cells themselves to have enhanced programming capability, thus maintaining energy efficiency while improving programming precision.
Solution Approach 2:
The patent implements a feedback mechanism where programmed memory values are read and verified against expected values. If verification fails, the system can re-program the cells with adjusted parameters. This closed-loop feedback system ensures high programming precision while working with energy-efficient non-volatile memory technology.
2Use of energy by moving object
If non-volatile memory arrays are used for analog neuromorphic computing, then energy efficiency is improved, but reading and verifying stored values deteriorates
Solution Approach 1:
The patent introduces a dedicated read and verify circuit as an intermediary between the non-volatile memory array and the processing logic. This intermediary component simplifies the complex task of reading and verifying analog values from memory cells, making it easier to detect and measure stored weights without compromising the energy efficiency of the non-volatile memory technology.
3Measurement precision
If separate multiplication and addition logic circuits are implemented, then computational accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges multiplication and addition operations into a single unified process by utilizing the inherent properties of non-volatile memory cells. The memory cells perform analog multiplication through conductance modulation, and the resulting currents are naturally summed at the bitline nodes, eliminating the need for separate digital multiplication and addition logic circuits while maintaining computational accuracy.
Solution Approach 2:
The non-volatile memory cell serves multiple functions: it stores weights, performs multiplication through conductance modulation, and enables addition through current summation. This multi-functional approach reduces device complexity by eliminating the need for dedicated multiplication and addition logic circuits, as the memory array itself performs these computational tasks.
4Ease of manufacture
If bulk CMOS technology is used, then manufacturing ease is improved, but synapse size becomes too large
Solution Approach 1:
The patent changes the operating parameters of CMOS technology by utilizing non-volatile memory cells in analog mode rather than digital mode. This parameter change allows each memory cell to represent multiple weight values through continuous conductance modulation, dramatically reducing the number of cells required per synapse and thus reducing overall synapse size while maintaining compatibility with standard CMOS manufacturing processes.
Data Source
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AI summary
Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.