Analog Neural Memory Array with Constant Source Impedance
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Solution Overview
Problem
Existing analog neural memory arrays face challenges with varying source impedance and power consumption across memory cells, leading to precision issues and susceptibility to noise during read, program, or erase operations.
Innovation Solution
The implementation of an analog neural memory array with approximately constant source impedance across each memory cell, achieved through a design that includes dummy bit lines and source line pulldown cells to maintain consistent impedance and power consumption, regardless of the selected cell or cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory array design is used, then device complexity is reduced, but source impedance varies across memory cells leading to precision issues
Solution Approach 1:
The bit line is segmented into multiple bit line segments, with each segment connected to a specific memory cell. Dummy bit line segments are added to ensure that each memory cell has a consistent total number of series-connected bit line segments, thereby maintaining constant source impedance across all cells while preserving reading precision.
Solution Approach 2:
Different portions of the memory array are configured with locally adapted structures. Specifically, memory cells in different rows or columns may have different numbers of actual bit line connections, but dummy bit line segments are strategically added to local regions to ensure uniform total segment count across all cells, achieving local impedance matching.
2Reliability
If conventional memory array design is used, then manufacturing simplicity is maintained, but power consumption varies across memory cells leading to noise susceptibility
Solution Approach 1:
The bit line is divided into multiple segments, and dummy bit line segments are introduced to ensure that each memory cell operates with a consistent number of series-connected segments. This segmentation approach equalizes power consumption across all memory cells, reducing noise susceptibility while maintaining manufacturing feasibility through systematic structure repetition.
Solution Approach 2:
The electrical parameters of the memory array are standardized by ensuring that each memory cell has the same total number of bit line segments in series. This parameter uniformity (number of segments) directly controls power consumption characteristics, making all cells have similar power draw and noise susceptibility despite differences in physical layout or connection patterns.
3Measurement precision
If memory cells have varying source impedance, then array structure remains simple, but precision and noise susceptibility deteriorate
Solution Approach 1:
By segmenting the bit line into multiple sections and adding dummy segments, the patent creates a structured approach where each memory cell's total series resistance becomes uniform. This segmentation strategy directly addresses the harmful effect of varying source impedance by equalizing the electrical path length and resistance for all cells, thereby improving both precision and noise immunity.
Solution Approach 2:
The patent achieves equipotentiality in terms of source impedance by ensuring that all memory cells present the same equivalent resistance to the read circuit. Through the addition of dummy bit line segments, each cell's electrical characteristics are normalized, creating uniform operating conditions across the array that reduce noise susceptibility and improve measurement precision.
Data Source
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AI summary
Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.