On-Chip Neural Network Model Pinning for Low-Latency FPGA Nodes
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Solution Overview
Problem
Neural networks are expensive to deploy using general-purpose CPUs or GPUs, and GPUs provide increased throughput but suffer from poor latency.
Innovation Solution
A method for evaluating neural network models using a system with multiple interconnected nodes, each equipped with on-chip memory blocks and compute units, where the neural network model is partitioned into layers and loaded into on-chip memory for processing, allowing for efficient parallel processing and reduced latency by maintaining the model in memory until service interruption or model modification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If neural network models are deployed using general-purpose CPUs, then deployment flexibility is maintained, but computational cost and time consumption increase significantly
Solution Approach 1:
The system segments the neural network model into distinct layers and partitions coefficients into N by M matrices that can be independently loaded and processed. This segmentation allows selective loading of only necessary model components into on-chip memory, reducing overall deployment complexity while maintaining computational efficiency for the segmented processing tasks.
Solution Approach 2:
The patent introduces on-chip memory blocks as an intermediary between the compute units and external memory sources. This intermediary layer buffers coefficient data, allowing compute units to perform neural network operations without frequent external memory access, thereby improving computational efficiency while keeping the system architecture manageable.
2Productivity
If GPUs are used to increase throughput, then processing speed improves, but latency increases
Solution Approach 1:
The patent transitions from the conventional von Neumann architecture (single memory hierarchy) to a multi-dimensional memory architecture where on-chip memory blocks are distributed across multiple nodes in a network. This dimensional change allows simultaneous data access from multiple locations, improving both throughput and latency by parallelizing memory operations across the network dimension.
Solution Approach 2:
The system performs preliminary action by pre-loading neural network coefficient matrices into on-chip memory blocks before computation begins. This preliminary loading eliminates runtime memory access delays, reducing latency while maintaining high throughput through efficient in-memory processing operations.
3Loss of time
If on-chip memory blocks are frequently updated to maintain low latency, then response time improves, but memory utilization efficiency decreases
Solution Approach 1:
The patent applies local quality by maintaining different data in different on-chip memory blocks based on their specific usage requirements. Frequently accessed coefficient matrices are pinned to specific memory blocks, while other blocks store less frequently accessed data or intermediate results. This localized optimization improves response time for critical operations while maintaining overall memory utilization efficiency through differentiated storage strategies.
Data Source
AI summary
Systems and methods for neural network processing are provided. A method in a system comprising a plurality of nodes interconnected via a network, where each node includes a plurality of on-chip memory blocks and a plurality of compute units, is provided. The method includes upon service activation receiving an N by M matrix of coefficients corresponding to the neural network model. The method includes loading the coefficients corresponding to the neural network model into the plurality of the on-chip memory blocks for processing by the plurality of compute units. The method includes regardless of a utilization of the plurality of the on-chip memory blocks as part of an evaluation of the neural network model, maintaining the coefficients corresponding to the neural network model in the plurality of the on-chip memory blocks until the service is interrupted or the neural network model is modified or replaced.