Neural Network Accelerator Event Recording via Phase-Based Store Detection

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Solution Overview

Problem

Current computing environments, particularly those utilizing neural network accelerators, face challenges in efficiently recording and processing program events during instruction execution, leading to increased complexity and resource usage.

Innovation Solution

A computer program product that includes instructions to perform processing phases, with checks for data storage into a designated area, allowing for reduced checks by determining if a store occurred within a single phase, thereby optimizing resource usage and simplifying verification processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple checks are performed to detect stores into designated areas during neural network processing, then measurement precision of memory access events is improved, but device complexity increases

Engineering Contradiction:
Improvedetection accuracy of store operationsVSAvoidcomplexity of verification processing
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the verification process by dividing memory space into designated areas and processing functions into multiple phases. This segmentation allows the system to perform targeted checks only in relevant areas during specific phases, reducing the overall number of checks needed while maintaining detection accuracy. The designated area segmentation enables the processor to focus verification efforts on critical memory regions without examining entire memory spaces.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by establishing designated areas and phase definitions before neural network processing begins. The system pre-configures which memory areas require monitoring and which processing phases should trigger checks. This preliminary setup eliminates the need for exhaustive real-time verification during execution, as the framework for detection is already in place, reducing device complexity while maintaining measurement precision.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive verification of memory access patterns is performed, then reliability of program event recording is improved, but loss of time increases

Engineering Contradiction:
Improveaccuracy of program event recordingVSAvoidprocessing time overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic action by performing verification checks at specific intervals corresponding to processing phases rather than continuously monitoring every memory operation. The system checks for store operations into designated areas at defined phase boundaries, providing reliable program event recording while minimizing time overhead by avoiding constant verification. This periodic approach balances reliability with efficient processing.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

By pre-defining designated areas and processing phases before execution, the system establishes a verification framework that enables reliable event recording without real-time computational overhead. The preliminary configuration of monitoring parameters allows the processor to efficiently determine whether checks are needed during phase transitions, reducing time loss while maintaining recording reliability.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If frequent checks are performed to detect stores into designated areas, then measurement precision is improved, but productivity decreases

Engineering Contradiction:
Improvedetection precision of memory storesVSAvoidinstruction processing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments both the memory space into designated areas and the processing into phases, allowing verification to occur only at phase boundaries for relevant areas. This segmentation reduces the frequency of checks from every memory operation to only at phase transitions for designated areas, maintaining detection precision while preserving instruction processing speed and overall system productivity.

Inventive Principle:
Principle #1Segmentation

4Measurement precision

If detailed monitoring of each processing phase is implemented, then measurement precision of program events is improved, but device complexity increases

Engineering Contradiction:
Improveprecision of program event detectionVSAvoidcomplexity of monitoring mechanism
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and isolates the verification logic into a separate mechanism that operates independently from the main neural network processing. The designated area monitoring and phase-based check determination are extracted as distinct functions, allowing detailed monitoring of program events without adding complexity to the core processing pipeline. This extraction enables precise event detection while keeping the monitoring mechanism modular and manageable.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12008395B2Program event recording storage alteration processing for a neural network accelerator instruction
Publication Date: 2024.06.11 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12008395B2 patent drawing
  • US12008395B2 patent drawing
  • US12008395B2 patent drawing

AI summary

Instruction processing is performed for an instruction. The instruction is configured to perform a function, which is to be performed in a plurality of processing phases. A processing phase is defined to store up to a selected amount of data. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of the function. Based on determining that the store into the designated area occurred, an interrupt is presented.