Neural Network Address Recommender for SSD Read Latency
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Solution Overview
Problem
Conventional SSDs face challenges in maximizing read performance due to random read request patterns and the inability to perform parallel read operations across multiple dies or planes, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A data storage device equipped with an address recommending circuit that utilizes a neural network to determine optimal unit storage spaces for write requests, generating feature data based on request information and stored data addresses to enhance internal parallelism and improve read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional address allocation methods are used considering only channel, package, die, and plane levels, then write operations can be distributed in parallel, but future read request patterns cannot be predicted leading to suboptimal parallelism utilization
Solution Approach 1:
The system performs preliminary actions by analyzing write request patterns and pre-determining optimal die allocation strategies before read requests arrive. The address recommending circuit uses historical write data to predict future read patterns and pre-optimizes data distribution across dies, enabling faster parallel read operations when requests are actually received.
Solution Approach 2:
The system implements feedback mechanisms where the address recommending circuit continuously monitors write request patterns, read performance metrics, and die utilization statistics. This feedback is used to dynamically adjust address allocation decisions and retrain the neural network model, improving the system's ability to predict and optimize for future read operations while adapting to changing workload patterns.
2Productivity
If data is stored in random address patterns typical of read requests, then read requests must be processed sequentially, but parallel processing capabilities across multiple dies and planes cannot be utilized
Solution Approach 1:
The system segments the storage address space across multiple dies and planes in an optimized manner using the address recommending circuit. By intelligently distributing data segments across different dies based on predicted read patterns, the system enables parallel processing of read requests that would otherwise need to be handled sequentially, reducing read latency while maximizing parallel processing capability.
3Productivity
If DRAM buffer is used to hide write delays, then write performance is improved, but read delays cannot be hidden as data must wait in the buffer before being output
Solution Approach 1:
The address recommending circuit performs preliminary actions by pre-optimizing data placement across dies based on predicted read patterns. This allows read data to be immediately available from the optimized distribution across multiple dies, eliminating the waiting delay that occurs when data must be transferred through the DRAM buffer, while write performance is maintained through parallel write operations to multiple dies.
Data Source
AI summary
A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.