Neural Network Arithmetic Apparatus Circuit Size Reduction
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Solution Overview
Problem
Conventional arithmetic processing apparatuses using convolutional neural networks require large circuit sizes due to the need for multiple convolution and activation components to process all data in one cycle, leading to inefficiencies in size and resource utilization.
Innovation Solution
The apparatus reduces circuit size by having the convolution arithmetic portion output only part of the required data for pooling processing in each cycle, with the pooling portion processing these results before activation, thereby reducing the number of components needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all convolution arithmetic result data required for one pooling processing are obtained in one arithmetic cycle, then the processing speed is improved, but the circuit size enlarges due to requiring multiple convolution arithmetic portions and multiple activation means
Solution Approach 1:
The patent segments the processing of convolution arithmetic result data across multiple arithmetic cycles. Instead of processing all data in one cycle, the system divides the work into stages, outputting a part of the required data in each cycle. This segmentation allows the use of a single convolution arithmetic portion and a single activation means to handle the entire dataset over time, thereby reducing circuit size while maintaining processing capability.
Solution Approach 2:
The patent implements periodic action by repeatedly executing the convolution arithmetic and activation processing across multiple arithmetic cycles. The single convolution arithmetic portion and activation means operate periodically, processing different portions of the data in each cycle until all required data are generated and pooled. This periodic operation enables the system to achieve the same overall processing result with fewer hardware components.
2Productivity
If multiple activation means are provided according to the number of required convolution arithmetic result data, then all data can be activated in one cycle, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the activation processing task across multiple arithmetic cycles instead of requiring multiple parallel activation means. A single activation means processes data sequentially over time, activating different portions of the convolution arithmetic result data in each cycle. This approach maintains full data processing capability while reducing the number of activation components from multiple to one.
Solution Approach 2:
The single activation means in the patent performs multiple functions across different arithmetic cycles, activating different sets of data in each cycle. This universal component replaces what would otherwise require multiple specialized activation means operating in parallel, thereby reducing device complexity while maintaining the ability to process all required data.
Data Source
AI summary
An arithmetic processing apparatus performs arithmetic by a neural network in which multiple processing layers are hierarchically connected. The arithmetic processing apparatus corresponding to one of the multiple processing layers includes a convolution arithmetic portion and a pooling processing portion. The convolution arithmetic portion receives an input data from another of the plurality of processing layers, performs convolution arithmetic to the input data, and in each arithmetic cycle, outputs a part of all convolution arithmetic result data required for single pooling processing. The pooling processing portion performs the single pooling processing to the all convolution arithmetic result data before executing activation processing.