Neural Network Chip De-Convolution Hardware Circuit
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Solution Overview
Problem
Conventional software-based de-convolution operations are inefficient, requiring significant memory storage and system bandwidth due to the need for zero-padding and expansion of feature maps, which hinders performance in high-demand AI scenarios.
Innovation Solution
A neural network chip with a memory and data reading circuit that performs expansion and zero-padding operations on feature maps and sends the padded data directly to a convolution calculating unit for calculation, eliminating the need for intermediate data storage in memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software is used to implement de-convolution operation, then flexibility and programmability are improved, but processing efficiency deteriorates
Solution Approach 1:
The patent replaces software-based de-convolution processing with a dedicated hardware circuit that performs the operation through parallel computing units. The hardware circuit includes multiple computing units that can simultaneously process different elements of the feature map, transforming the sequential software operation into parallel hardware execution, thereby dramatically improving processing efficiency while maintaining the required functionality
Solution Approach 2:
The patent changes the operational parameters by configuring the hardware circuit with adjustable parameters such as kernel size, stride, and padding values. This allows the same hardware circuit to adapt to different de-convolution configurations through parameter reconfiguration rather than requiring different software implementations, thus maintaining flexibility while achieving hardware-level performance
2Device complexity
If zero-padding and expansion operation is performed using software, then implementation simplicity is improved, but memory usage and system bandwidth increase
Solution Approach 1:
The patent introduces a new dimension of processing by performing zero-padding and expansion operations directly within the computing units through data replication and positioning logic, rather than storing expanded data in memory. The hardware circuit generates padded values on-the-fly during computation, transforming a memory-intensive operation into a computation-intensive operation that uses minimal memory bandwidth
Solution Approach 2:
The patent implements preliminary action by pre-configuring the hardware circuit with the padding and expansion rules before processing begins. The circuit is designed to automatically apply the correct padding values and data positioning based on pre-set parameters, eliminating the need for separate software-based preparation steps and reducing memory access requirements
Data Source
AI summary
A neural network chip and a related product are provided. The neural network chip (103) includes: a memory (102), a data reading/writing circuit, a convolution calculation circuit, wherein the memory is used for storing a feature map; the data reading/writing circuit is used for reading the feature map from the memory and execute an expansion and zero-padding operation on the feature according to configuration information of the feature map, and sending to the convolution calculation circuit (S401); and the convolution calculation circuit is used for performing convolution calculation on the data obtained after the expansion and zero-padding operation to implement a de-convolution operation (S402). The technical solution has advantages of saving memory usage and bandwidth.