Neural Network Circuit Abstraction for RTL to TLM Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of designing and verifying modern integrated circuits, particularly in system-on-chip solutions, is hindered by the time-consuming process of simulating design changes, which often requires converting existing Register Transfer Level (RTL) models to higher-level Transaction Level Modeling (TLM) for efficient design exploration and verification, without effective tools to elevate abstraction levels.
Innovation Solution
A system and method that utilizes neural networks and machine learning algorithms to generate an abstract model of a circuit's timing behavior, allowing conversion from a lower-level RTL description to a higher-level TLM description, thereby simplifying design exploration and simulation by approximating circuit behavior with weighted equations and causality analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation is performed to test and explore design changes, then design verification is improved, but time consumption increases significantly
Solution Approach 1:
The patent creates an abstract model that copies the essential timing behavior of the original RTL circuit without replicating its full structural complexity. This abstract model serves as a simplified representation that can be simulated much faster while preserving the critical timing characteristics needed for design verification.
Solution Approach 2:
The patent segments the circuit analysis into two parts: structural analysis (performed once on the original RTL) and timing behavior analysis (performed on the abstract model). This segmentation allows the time-consuming simulation to be performed only on the simplified abstract model rather than the full complex circuit.
2Productivity
If design is performed at higher level of abstraction (TLM), then design exploration efficiency is improved, but conversion from RTL to TLM is complex
Solution Approach 1:
The patent introduces an intermediary abstract model that bridges RTL and TLM representations. This intermediate representation captures timing behavior in a simplified form that can be automatically generated from RTL and then used for efficient TLM-level design exploration, avoiding the complexity of direct conversion.
Solution Approach 2:
The patent changes the parameters represented in the model from detailed structural parameters in RTL to aggregated timing parameters in the abstract model. This parameter transformation simplifies the representation while preserving the essential timing characteristics needed for design exploration.
3Measurement precision
If existing RTL models are used without conversion, then model accuracy is maintained, but simulation speed is slow
Solution Approach 1:
The patent creates a simplified copy of the RTL model that preserves timing behavior characteristics while removing unnecessary structural details. This abstract copy maintains accuracy for timing analysis purposes while enabling much faster simulation.
Solution Approach 2:
The patent extracts only the essential timing behavior from the full RTL model, separating it from the detailed structural information. This extraction creates a minimal model that contains just the timing characteristics needed for verification, eliminating the simulation overhead of the complete RTL description.
Data Source
AI summary
A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the abstraction level. By changing the abstraction level, the conversion is not simply a code conversion from one language to another, but a process of learning the circuit using neural networks and representing the circuit using a system of equations that approximate the circuit behavior, particularly with respect to timing aspects. A higher level of abstraction eliminates much of the particular implementation details, and allows easier and faster design exploration, analysis, and test, before implementation. In one aspect, a model description of the circuit, protocol information relating to the circuit, and simulation data associated with the lower level description of the circuit are used to generate an abstract model of the circuit that approximates the circuit behavior.