Neural Network Circuit Arithmetic Operation Control Signal Generation
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Solution Overview
Problem
Current semiconductor devices face inefficiencies in executing arithmetic operations within neural networks, particularly in generating and processing core and peripheral data, which affects the speed and efficiency of neural network computations.
Innovation Solution
Incorporating an operation control signal generation circuit and a neural network circuit that generates arithmetic signals and read signals based on commands, allowing for the selection and processing of core and peripheral data to perform arithmetic operations, thereby enhancing the efficiency and speed of neural network computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional semiconductor devices are used for neural network arithmetic operations, then device structure is simple, but computational speed and efficiency are insufficient
Solution Approach 1:
The semiconductor device is divided into distinct functional regions: a core region containing first and second core data, a peripheral region containing peripheral data, and dedicated circuits for each function. This segmentation allows parallel processing of different data types while maintaining clear signal paths, thereby improving computational speed without creating an overly complex monolithic structure.
Solution Approach 2:
The patent introduces a spatial dimension to data organization by separating core data and peripheral data into different regions (core region vs. peripheral region). This dimensional separation enables simultaneous access and processing of different data types through region-specific read signals, enhancing computational efficiency while keeping the overall device architecture manageable.
2Productivity
If core data and peripheral data are processed separately through different read signals, then data processing efficiency is improved, but control signal complexity increases
Solution Approach 1:
The operation control signal generation circuit serves multiple functions: it generates both the first read signal for core data and the second read signal for peripheral data, as well as the arithmetic operation control signal. This multi-functionality allows efficient data processing through a single control circuit, avoiding the need for separate control circuits for each function and thus limiting the increase in control signal complexity.
Solution Approach 2:
The operation control signal generation circuit preliminarily generates all necessary control signals (first read signal, second read signal, and arithmetic operation control signal) based on a single command signal before the actual data processing occurs. This preliminary generation of control signals streamlines the subsequent data processing operations and reduces the real-time control complexity during computation.
3Measurement precision
If arithmetic operation control signals are generated based on multiple commands and comparison pulses, then operational precision is improved, but signal generation complexity increases
Solution Approach 1:
The operation control signal generation circuit uses feedback from comparison pulses (generated by comparing count codes with target codes) to adjust and generate precise arithmetic operation control signals. This feedback mechanism ensures that the control signals are generated with high precision based on actual computational needs, while the feedback loop is managed by existing circuit components rather than adding substantial new complexity.
Data Source
AI summary
A semiconductor device includes an operation control signal generation circuit and a neural network circuit. The operation control signal generation circuit generates an arithmetic signal and a core read signal based on a command. The neural network circuit outputs first core data and second core data from a core region based on the core read signal, a cell block selection signal, and a cell selection signal. The neural network circuit also performs an arithmetic operation of the first and second core data based on the arithmetic signal to generate arithmetic result data.