Neural Network Circuit with Context-Switching Arithmetic Units
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Solution Overview
Problem
Deep learning neural network circuits face challenges in maintaining recognition accuracy while preventing increases in circuit size and power consumption, particularly due to the high frequency of product-sum operations.
Innovation Solution
A neural network circuit design incorporating multiple arithmetic circuits with programmable switch elements and oxide semiconductor transistors, allowing for efficient product-sum operations and context-switching to perform different processes using the same circuit resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of intermediate layers is increased to improve recognition accuracy, then recognition accuracy is improved, but circuit size increases
Solution Approach 1:
The patent implements a shared arithmetic circuit structure where a single arithmetic circuit performs product-sum operations for multiple different intermediate layers by switching its function based on control signals. This allows the same hardware resources to be reused across different layers, enabling deep learning architectures with multiple intermediate layers without proportionally increasing circuit size.
Solution Approach 2:
The patent introduces dynamic switching mechanisms including context signal input to memory circuits and switch element control that allow the arithmetic circuit to adaptively change its operation mode and data pathways. This dynamic reconfiguration enables the circuit to handle different computational tasks for different layers, maximizing resource utilization while maintaining the capability for deep architectures.
2Measurement precision
If the number of intermediate layers is increased to improve recognition accuracy, then recognition accuracy is improved, but power consumption increases
Solution Approach 1:
By designing the arithmetic circuit to serve multiple intermediate layers through function switching, the patent eliminates the need for separate dedicated arithmetic circuits for each layer. This reuse of computational resources across layers significantly reduces the total power consumption compared to having independent arithmetic circuits for every intermediate layer in a deep network.
Solution Approach 2:
The patent implements a mechanism where the arithmetic circuit discards its previous computational state and recovers/reconfigures for new computational tasks through context signal switching. This allows the same physical circuit to be reused for different layers by clearing prior state and loading new parameters, thereby avoiding the continuous power consumption that would result from maintaining multiple active circuits simultaneously.
3Area of stationary object
If product-sum operations are performed efficiently to prevent circuit size increase, then circuit size is controlled, but resource utilization for different processes becomes challenging
Solution Approach 1:
The patent employs dynamic control mechanisms including context signals and switch elements that enable the arithmetic circuit to flexibly reconfigure its data pathways and operational parameters. This dynamic adaptability allows the same circuit resources to be efficiently allocated to different computational processes and intermediate layers, solving the resource utilization challenge while maintaining compact circuit size.
Solution Approach 2:
The patent changes operational parameters such as weight data, input data, and control signals to adapt the arithmetic circuit for different computational tasks. By modifying these parameters rather than changing the physical circuit structure, the system achieves versatile resource utilization across different processes while maintaining a fixed, compact circuit architecture.
Data Source
AI summary
A neural network circuit having a novel structure is provided.A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.