Neural Network Circuit Dynamic Delay Control
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Solution Overview
Problem
Existing neural network computation circuits face challenges in increasing the speed of neuron computation due to the need for a fixed long delay time for setting up word lines, which is determined by the total number of word lines in the memory array, making it difficult to achieve high-speed operations.
Innovation Solution
A neural network computation circuit with a control circuit that includes a selected word-line count management circuit and a timing generation circuit, which dynamically sets a delay time based on the actual number of selected word lines, allowing for dynamic adjustment of the delay time and eliminating the need for a fixed long delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed long delay time is set for word line setup, then the word lines can be properly initialized, but the computation speed is reduced
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed delay time to a variable delay time that adapts based on the number of selected word lines. The delay time is dynamically adjusted according to the actual computation requirements, allowing the system to optimize between initialization reliability and computation speed for different operational scenarios.
Solution Approach 2:
The patent changes the parameter of delay time from a static fixed value to a dynamic variable value. By modifying the delay time parameter based on the number of selected word lines, the system can properly initialize word lines when needed while enabling faster computation when fewer word lines are selected, thus resolving the contradiction between reliability and speed.
2Reliability
If the delay time is determined by the total number of word lines, then all word lines can be ensured to be ready, but the computation speed cannot be increased
Solution Approach 1:
The patent applies partial action by considering only the number of actually selected word lines rather than all possible word lines when determining the delay time. This allows the system to ensure readiness only for the word lines that will be used in the current computation, avoiding unnecessary delays for unused word lines and thereby increasing computation throughput.
Solution Approach 2:
The system dynamically adjusts the delay time based on the actual number of selected word lines, transforming the static delay mechanism into a dynamic one. This enables the system to optimize word line readiness for each specific computation task, improving productivity by avoiding fixed long delays when fewer word lines are needed.
3Device complexity
If a fixed delay time is used for all computation operations, then the control circuit is simple, but the computation speed cannot be optimized for different scenarios
Solution Approach 1:
The patent changes the delay time parameter from fixed to variable, allowing the control circuit to adapt to different computation scenarios. Although this introduces some complexity in the control logic, it enables significant speed optimization by adjusting the delay time according to the number of selected word lines, achieving a balance between complexity and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed neuron computation by adjusting the delay time according to the actual number of selected word lines, thereby improving the speed of neural network operations without the necessity of setting a fixed long delay time.
Implementation Method 1
a computation circuit that performs, by using current flowing through the one or more bit lines selected by the column selection circuit, a multiply-accumulate operation on connection weight coefficients held in two or more memory cells
Data Source
AI summary
A neural network computation circuit includes: a plurality of word lines; a plurality of memory cells; a word-line drive circuit; a column selection circuit; a computation circuit that performs neuron computation; a word-line selected-state signal generation circuit; a timing generation circuit; a computation-result processing circuit; and a selected word-line count management circuit that manages a selected word-line count that is information relevant to a total number of word lines that are placed in a selected state when a multiply-accumulate operation is performed, and transmits the selected word-line count to the timing generation circuit. The timing generation circuit sets, according to the selected word-line count, a delay time from when a word-line activation signal is output until when a computation-circuit control signal is output.