Neural Network Circuit Using Non-Volatile Memory for Multiply-Accumulate Operations
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Solution Overview
Problem
Conventional neural network computation circuits require large-capacity memory, register, multiplication, and accumulator circuits, leading to high power consumption and increased chip area, and face challenges in integrating large-scale neural networks due to the need for analog-digital conversion and complex control circuits.
Innovation Solution
A neural network computation circuit utilizing non-volatile semiconductor memory elements that perform multiply-accumulate operations using current values, eliminating the need for large-capacity memory and multiplication circuits, and allowing digital data transmission between neurons, thereby reducing power consumption and enabling large-scale integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional digital circuits are used for neural network computation, then computation speed can be maintained, but power consumption increases and chip area expands due to large-capacity memory, register, multiplication, and accumulator circuits
Solution Approach 1:
The patent merges the functions of memory and computation into a single architecture where non-volatile memory elements directly perform multiply-accumulate operations. The memory cells store connection weights and simultaneously compute products with input signals, eliminating separate multiplication and accumulation circuits. This fusion reduces power consumption while maintaining computational capability.
Solution Approach 2:
The patent extracts the computation function from traditional digital logic circuits and relocates it to the memory elements themselves. By using the resistive properties of non-volatile memory cells to perform analog multiplication and accumulation, the design removes the need for separate multiplication circuits and large-capacity registers, thereby reducing overall power consumption.
2Productivity
If conventional digital circuits are used for neural network computation, then computation functionality is achieved, but chip area increases due to large-capacity memory, register, multiplication, and accumulator circuits
Solution Approach 1:
The patent combines memory storage and computation functions into the same physical structure. Non-volatile memory cells store connection weights and perform multiply-accumulate operations simultaneously, eliminating the need for separate multiplication circuits, accumulator circuits, and large-capacity registers. This integration dramatically reduces chip area while preserving full computation functionality.
Solution Approach 2:
The non-volatile memory elements serve multiple functions: they store connection weights, perform analog multiplication with input signals, accumulate products through parallel current summation, and maintain data persistently. This multi-functionality replaces multiple specialized circuits with a single versatile memory-based computing unit, reducing chip area.
3Use of energy by moving object
If analog resistance values are used in non-volatile memory elements, then power consumption is reduced, but integration of large-scale neural networks becomes difficult due to the need for analog-digital conversion
Solution Approach 1:
The patent segments the neural network computation into independent memory cell units that each perform local multiply-accumulate operations. By organizing memory cells in arrays where each cell handles specific weight-input computations in parallel, the design avoids the need for centralized analog-digital conversion, reducing integration complexity while maintaining low power consumption.
4Use of energy by moving object
If non-volatile semiconductor memory elements are used for current-based operations, then power consumption is reduced and chip area is minimized, but the circuit requires novel architecture to eliminate large-capacity memory and multiplication circuits
Solution Approach 1:
The patent replaces traditional digital logic circuits with physics-based analog computation using the electrical properties of non-volatile memory elements. Instead of using transistors and logic gates for multiplication and accumulation, the design utilizes the resistive characteristics of memory cells to perform computations directly, simplifying the overall circuit architecture despite requiring novel design approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption and chip area while facilitating the integration of large-scale neural networks by using non-volatile semiconductor memory elements for current-based operations, enabling efficient digital data transmission and computation.
Implementation Method 1
The neural network computation circuit stores connection weight coefficients in non-volatile memory elements and applies analog voltage values equivalent to inputs to the non-volatile memory elements, obtaining analog current values as results of multiply-accumulate operations
Data Source
AI summary
A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.