Neural Network Circuitry With In-Memory MAC Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In von Neumann computer architectures, frequent data movements between processors and memory lead to performance delays and high power consumption, particularly in deep neural network operations, which are often handled by combinations of CPUs, GPUs, and ASICs, limiting chip performance.
Innovation Solution
An electronic device with neural network circuitry that includes synaptic memory cells, reference memory cells, and neuron circuits, where the neuron circuits generate output signals based on column and reference signals, determine start voltages for integration, and perform leakage or firing operations based on integrated voltages, utilizing resistive memory elements with different resistance values to optimize neural network operations directly in memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is frequently moved between processor and memory in von Neumann architecture, then computational operations can be performed, but power consumption increases and performance delays occur
Solution Approach 1:
The patent merges memory storage and computational processing into a single integrated structure. Memory cells store synaptic weights and simultaneously perform MAC operations and activation functions through circuit elements connected within the memory array, eliminating the need to move data between separate processor and memory components.
Solution Approach 2:
The patent introduces specialized neural network circuitry as an intermediary between traditional memory and processor. This circuitry includes memory cells with integrated MAC units and activation function circuits that mediate computational operations directly at the memory location, reducing data transfer requirements while maintaining computational capability.
2Productivity
If data is frequently moved between processor and memory in von Neumann architecture, then computational operations can be performed, but computational speed is limited due to data transfer delays
Solution Approach 1:
The patent merges memory storage and computational processing into a single integrated structure. Memory cells store synaptic weights and simultaneously perform MAC operations and activation functions through circuit elements connected within the memory array, eliminating the need to move data between separate processor and memory components.
Solution Approach 2:
The patent segments the neural network computation into distinct functional units distributed across the memory array: weight storage in memory cells, MAC operations in dedicated circuitry, and activation functions in separate circuits. This segmentation allows parallel execution of multiple operations simultaneously at different memory locations.
3Adaptability or versatility
If traditional processor combinations (CPU, GPU, ASIC) are used for deep neural network operations, then computational flexibility is maintained, but chip performance is limited
Solution Approach 1:
The patent creates a universal memory-based computing platform that can perform multiple neural network operations (MAC, activation functions, weight updates) within the same integrated structure. The memory cells and associated circuitry can handle different types of neural network computations without requiring separate specialized hardware for each operation type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances neural network performance by enabling efficient in-memory operations, improving the speed and efficiency of neural network computations while minimizing data transfer delays.
Implementation Method 1
The memory element may be configured to have a first resistance value at one time and a second resistance value at another time
Data Source
AI summary
An electronic device with neural network circuitry is provided. The neural network circuit includes a synaptic memory cell including a memory element disposed along an output line and configured to, dependent on the memory element and an input signal applied to an input line, generate a column signal on the output line; a reference memory cell comprising a reference memory element disposed along a reference line, and configured to, dependent on the reference memory element and the input signal, generate a reference signal on the reference line; and a first neuron circuit configured to generate an output signal based on the column signal and the reference signal, and determine a start voltage of an integration to be performed based on the output signal in response to a previous firing by the first neuron circuit with respect to a previous input signal or another firing performed by a second neuron circuit.