Neural Network Circuit Clock Gating for Embedded IoT
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Solution Overview
Problem
Convolutional neural networks (CNNs) face challenges in being embedded in IoT devices due to the difficulty of implementing large-scale dedicated circuits and achieving sufficient operational performance with limited hardware resources such as CPU or memory.
Innovation Solution
A neural network circuit with a convolution operation circuit and a quantization operation circuit that performs clock gating, allowing for efficient operation by partitioning data and utilizing low-bit data types, reducing hardware requirements and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large-scale dedicated circuits are used to implement convolutional neural networks, then operational performance is improved, but device complexity and embeddability worsen
Solution Approach 1:
The patent changes the numerical parameters of data representation by using low-bit data types (e.g., 4-bit or lower precision) instead of traditional high-precision formats. This parameter change reduces the hardware resources needed for storage and processing while maintaining sufficient operational performance for embedded devices.
Solution Approach 2:
The patent segments the neural network processing into distinct functional blocks (convolution operation circuit, quantization operation circuit, activation function circuit) that can be selectively activated. This segmentation allows the system to achieve high performance when needed while reducing complexity by activating only necessary blocks during different operation phases.
2Productivity
If more hardware resources (CPU, memory) are allocated to neural network operations, then operational performance is improved, but device resource requirements worsen
Solution Approach 1:
The patent fundamentally changes the data precision parameter from traditional 32-bit floating-point to low-bit representations (4-bit or lower), which directly reduces the quantity of memory resources and computational resources required while maintaining acceptable operational performance for embedded applications.
Solution Approach 2:
The patent employs simplified computational structures that use less expensive hardware resources, accepting that individual computational operations may require multiple steps or iterations, thereby trading resource quantity for operational adequacy in embedded contexts.
3Use of energy by stationary object
If clock gating is enabled during waiting periods, then power consumption is reduced, but operational responsiveness may worsen
Solution Approach 1:
The patent implements periodic clock gating that rhythmically enables and disables clock signals to circuit blocks based on their operational state. During waiting periods when blocks are idle, clocks are gated off to reduce power consumption, while quickly resuming when operations are needed, creating a periodic pattern that balances power savings with operational responsiveness.
Data Source
AI summary
A neural network circuit provided with a convolution operation circuit that performs a convolution operation on input data, and a quantization operation circuit that performs a quantization operation on convolution operation output data from the convolution operation circuit, wherein the convolution operation circuit, when waiting to execute the convolution operation, enables clock gating of a first clock supplied to at least a portion of the convolution operation circuit.