Neural Network Closed-Loop Path Multitask Parallel Processing

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Solution Overview

Problem

Neural networks with closed-loop paths suffer from low processing efficiency due to single-task computation mode, leading to prolonged data processing times.

Innovation Solution

A multitask parallel processing method and apparatus that input data sequences into neural networks as data packets, allowing nodes in the closed-loop path to compute all data in a packet simultaneously, reducing computation preparation times and enhancing processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If single-task computation mode is adopted in closed-loop path, then computation accuracy is maintained, but processing efficiency deteriorates and data processing time is prolonged

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddata processing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the computation process by introducing computation flow identifiers and dividing data packets into multiple pieces, allowing different computation flows to process different data pieces in parallel while maintaining the closed-loop path integrity. This segmentation enables multi-task processing without compromising computation accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a new dimension to the computation process by introducing computation flow identifiers as an additional parameter dimension. This allows the system to track and manage multiple computation flows simultaneously, transforming the single-task sequential processing into multi-task parallel processing while maintaining the original computation logic.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple computation flows are started frequently, then processing parallelism is improved, but computation preparation time increases and efficiency deteriorates

Engineering Contradiction:
Improveprocessing parallelismVSAvoidcomputation preparation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-allocating computation flow identifiers and preparing computation contexts before actual data processing begins. This allows the system to minimize computation preparation time during runtime by having resources ready in advance, enabling faster startup of parallel computation flows.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The computation flow identifier mechanism serves multiple functions: it tracks computation progress, manages data packet routing, coordinates feedback paths, and enables parallel processing. This universal mechanism reduces the need for separate preparation systems for each function, thereby reducing overall computation preparation time.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If parallel task number is not properly selected, then processing speed may increase, but computation errors occur

Engineering Contradiction:
Improveprocessing speedVSAvoidcomputation accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where computation results are routed back to previous nodes based on computation flow identifiers and data packet tracking. This feedback system allows the network to verify computation accuracy and correct errors, ensuring reliability even when multiple parallel tasks are executed simultaneously.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The computation flow identifier acts as an intermediary that coordinates between multiple parallel computation tasks and the closed-loop path. It ensures that each task is properly tracked, routed, and verified, preventing computation errors while maintaining high processing speed through parallel execution.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11392426B2Multitask parallel processing method and apparatus, computer device and storage medium
Publication Date: 2022.07.19 LYNXI TECH CO LTD
  • US11392426B2 patent drawing
  • US11392426B2 patent drawing
  • US11392426B2 patent drawing

AI summary

Embodiments of the present disclosure provide multitask parallel processing method and apparatus, a computer device and a storage medium. The method is applied to a neural network consisting of a plurality of nodes, the neural network including at least one closed-loop path, and the method includes: inputting a data sequence to be computed into the neural network in a form of data packets, each of the data packets including multiple pieces of data; and computing, by the nodes in the closed-loop path, all the data in a currently received data packet each time a computation flow is started.