Neural Network Model Compression via Vector Register Association
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Solution Overview
Problem
Conventional methods for reducing the size of neural network models often compromise model accuracy or execution efficiency, as they fail to effectively balance the trade-off between model size reduction and execution efficiency, particularly due to limitations in existing accelerator architectures and pruning strategies.
Innovation Solution
The proposed solution involves compressing neural network data by pruning weight elements and associating the compressed data with vector registers, using variable-length vectors in the Instruction Set Architecture (ISA) to optimize data loading, and adjusting the structure of vector registers based on thresholds to ensure efficient data association and minimize accuracy loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional pruning methods are used to reduce model size, then the model size is reduced, but model accuracy or execution efficiency is compromised
Solution Approach 1:
The patent changes the parameter of data representation by compressing neural network data into variable-length vectors that can be efficiently mapped to vector registers. This compression transforms the data format without losing essential information, allowing reduced model size while preserving accuracy through optimal parameter encoding.
Solution Approach 2:
The patent introduces dynamic adjustment of vector register structures based on the compressed data characteristics. The system adaptively configures register allocations and vector lengths to match the pruned model's requirements, enabling flexible optimization that maintains execution efficiency and accuracy despite model size reduction.
2Quantity of substance
If aggressive pruning is applied to minimize model size, then model size reduction is maximized, but execution efficiency deteriorates
Solution Approach 1:
The patent optimizes execution efficiency by changing parameters such as vector register length, data layout, and memory access patterns to match the pruned model structure. These parameter adjustments ensure that the compressed model executes efficiently on vector processors despite the reduced number of parameters.
Solution Approach 2:
The patent creates a universal compression framework that works across different neural network architectures and pruning levels. The variable-length vector representation and adaptive register allocation can handle various model sizes and structures, maintaining execution efficiency regardless of the degree of pruning applied.
3Device complexity
If fixed-size vector registers are used, then hardware implementation is simpler, but adaptability to different model sizes is limited
Solution Approach 1:
The patent implements dynamic vector register structures that can adapt their size and configuration based on the input data and model requirements. This dynamic approach allows the same hardware to efficiently handle various model sizes by adjusting register allocations and vector lengths, providing both flexibility and performance.
Solution Approach 2:
The patent segments the vector register space into variable-length portions that can be dynamically allocated to different compressed data elements. This segmentation allows efficient utilization of register resources for pruned models with varying parameter counts, improving adaptability without requiring completely different hardware configurations.
Data Source
AI summary
Methods and apparatus for reducing a size of a neural network model, the method including: compressing data of the neural network model; identifying structure information of a vector register, wherein the structure information includes a number of registers included in the vector register; comparing a number of elements in the compressed data with a first condition, wherein the first condition is determined based on the number of registers in the vector register; and in response to the number of elements satisfying the first condition, associating the compressed data with the vector register to enable loading the compressed data to the vector register.