Sequentially Connected Neural Network Computation Modules
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Solution Overview
Problem
High-performance chips optimized for resource-demanding tasks often underutilize computational resources for less demanding tasks, leading to inefficiencies in neural network inference, while reconfigurable chips like FPGAs face limitations in peak compute performance due to resource-intensive reconfiguration and complex interconnects.
Innovation Solution
Implementing sequentially connected computation modules with reduced interconnects and a 'daisy-chain' approach to enable coarse-grained parallel reconfigurability, allowing direct access to memory and synchronized operations across modules, thereby optimizing resource utilization and reducing connection complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single chip is designed with computational resources to accommodate the most resource-demanding task, then peak performance for that task is improved, but resource utilization for other tasks deteriorates
Solution Approach 1:
The chip is divided into multiple independently controllable computation modules (CMs) that can be selectively activated. Each CM can be individually enabled or disabled based on the specific task requirements, allowing the system to scale computational resources dynamically rather than always deploying the full array of resources designed for peak performance scenarios.
Solution Approach 2:
The computation modules are designed with dynamic enable/disable capability through control logic that responds to task characteristics. This allows the system to adaptively configure the active computational resources based on the current workload, transitioning from a static all-or-nothing resource allocation to a dynamic, task-aware configuration that optimizes both peak performance and average utilization.
2Adaptability or versatility
If reconfigurable chips like FPGAs are used to improve adaptability for different neural network tasks, then versatility is improved, but peak compute performance deteriorates due to resource-intensive reconfiguration and complex interconnects
Solution Approach 1:
The system segments the computation into independent modules with standardized interfaces, allowing selective activation rather than full reconfiguration. This approach provides adaptability by enabling different subsets of modules to be used for different tasks without requiring the resource-intensive reconfiguration characteristic of FPGAs.
Solution Approach 2:
Each computation module is designed as a universal building block that can perform the same neural network operations (matrix multiplication, convolution) for different tasks. The modules share common data paths and control interfaces, eliminating the need for task-specific reconfiguration while maintaining versatility through flexible module selection and combination.
3Adaptability or versatility
If FPGAs implement fine-grained reconfigurability to support all degrees of parallelism, then adaptability is improved, but device complexity and resource requirements worsen
Solution Approach 1:
The system divides the computational workload into discrete, independently controllable modules arranged in a simplified interconnect topology. Rather than implementing complex fine-grained reconfiguration switches and routing logic, the segmented module approach provides parallelism support through selective module activation with straightforward data flow between adjacent modules.
Solution Approach 2:
Instead of using complex interconnects to enable fine-grained reconfiguration, the system inverts the approach by using simple, fixed interconnects between modules and achieving flexibility through the selective enabling/disabling of entire modules. This reverses the traditional FPGA paradigm of complex routing with simple functional units, opting for simple routing with selectively activated functional units.
Data Source
AI summary
Neural network hardware acceleration is performed by an integrated circuit including sequentially connected computation modules. Each computation module includes a processor and an adder. The processor includes circuitry configured to receive an input data value and a weight value, and perform a mathematical operation on the input data value and the weight value to produce a resultant data value. The adder includes circuitry configured to receive the resultant data value directly from the processor, receive one of a preceding resultant data value and a preceding sum value directly from a preceding adder of a preceding computation module, add the resultant data value to the one of the preceding resultant data value and the preceding sum value to produce a sum value, and transmit one of the resultant data value and the sum value to the memory or directly to a subsequent adder of a subsequent computation module.