Hardware Neural Network Conversion via Basic Unit Segmentation
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Solution Overview
Problem
Existing neural network hardware chips face challenges in supporting arbitrary neural network applications due to fixed-size matrix operations, lower precision, and inflexible activation functions, leading to performance bottlenecks and limited integration levels.
Innovation Solution
A hardware neural network conversion method that splits the neural network connection diagram into basic units with only ingress and egress nodes, reconstructs the network topology, and adjusts weight parameters to fulfill hardware constraints, allowing for efficient mapping onto hardware modules and supporting arbitrary neural network applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed-size matrix operations are used in hardware neural network chips, then hardware implementation efficiency is improved, but adaptability to arbitrary neural network applications deteriorates
Solution Approach 1:
The patent divides the neural network into multiple basic units, each containing only ingress nodes and egress nodes with full connections. This segmentation allows the hardware to process fixed-size matrix operations efficiently while the composition of multiple basic units can adapt to arbitrary neural network structures and sizes, thus resolving the contradiction between hardware efficiency and application adaptability.
2Device complexity
If lower precision is used in hardware neural network chips, then hardware complexity is reduced, but manufacturing precision of neural network functionality deteriorates
Solution Approach 1:
The patent adjusts weight parameters within basic units to fulfill hardware constraints while maintaining equivalent functionality. By optimizing parameter selection and using techniques like weight sharing and quantization, the system achieves acceptable precision with reduced hardware complexity, resolving the trade-off between hardware simplicity and functional accuracy.
3Device complexity
If inflexible activation functions are used in hardware neural network chips, then device complexity is reduced, but adaptability to different neural network applications deteriorates
Solution Approach 1:
The patent designs basic units with universal ingress and egress nodes that can accommodate different activation functions. The full connection structure between ingress and egress nodes allows the same hardware unit to implement various activation functions by reconfiguring weights and biases, providing multi-functionality without increasing device complexity, thus resolving the contradiction between simplicity and adaptability.
4Manufacturing precision
If neural network applications are tightly coupled with chip development, then manufacturing precision is improved, but device complexity and development time increase
Solution Approach 1:
The patent introduces basic units as an intermediary layer between arbitrary neural network applications and hardware implementation. These basic units serve as a standardized interface that decouples application development from chip development, allowing high-level neural network designs to be converted into hardware-compatible forms without direct coupling, thus reducing development complexity while maintaining precision.
Data Source
AI summary
A hardware neural network conversion method, a computing device, a compiling method and a neural network software and hardware collaboration system for converting a neural network application into a hardware neural network fulfilling a hardware constraint condition are disclosed. The method comprises: obtaining a neural network connection diagram corresponding to the neural network application; splitting the neural network connection diagram into neural network basic units; converting each of the neural network basic units so as to form a network having equivalent functions thereto and formed by connecting basic module virtual entities of neural network hardware; and connecting the obtained basic unit hardware network according to the sequence of splitting so as to create a parameter file for the hardware neural network. The present disclosure provides a novel neural network and a brain-like computing software and hardware system.