Neural Network Processor Crossbar Routing for Sparse Weight Processing
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Solution Overview
Problem
Artificial neural networks require extensive computational resources and power consumption due to the need for numerous multiply-accumulate operations across layers, especially in sparsely populated weight arrays, where many weights are zero, leading to inefficiencies in processing speed and energy use.
Innovation Solution
An integrated circuit with a SIMD array of processors and a crossbar architecture that selectively routes non-zero weighted inputs to processors, performing only necessary multiply-accumulate operations, thereby reducing power consumption and increasing processing speed by skipping zero-weighted inputs and processing neurons in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional neural network processing is used with full weight arrays, then computational completeness is maintained, but power consumption increases and processing speed decreases due to numerous multiply-accumulate operations on zero weights
Solution Approach 1:
The patent extracts only the non-zero weights from the full weight array and processes them selectively through the crossbar architecture. By removing zero-weight connections from the computation graph, the system reduces the number of multiply-accumulate operations while maintaining the essential computational function of the neural network layer.
Solution Approach 2:
Instead of performing complete multiply-accumulate operations on all weight entries including zeros, the system applies partial action by computing only the necessary operations for non-zero weights. This selective computation approach reduces energy consumption and increases processing speed without sacrificing computational accuracy.
2Productivity
If all input values are processed through every processor, then computational thoroughness is maintained, but the number of multiply-accumulate cycles increases, reducing processing speed
Solution Approach 1:
The crossbar architecture dynamically routes input values to processors based on the sparsity pattern of weights. The system adapts the computation path in real-time, directing data only to processors that have non-zero weights for the current operation, thereby reducing the total number of multiply-accumulate cycles required.
Solution Approach 2:
The system extracts and processes only the essential computational operations corresponding to non-zero weights, removing redundant operations associated with zero weights from the processing pipeline. This extraction reduces the total number of cycles while maintaining computational correctness.
3Use of energy by moving object
If a crossbar architecture with selective routing is implemented, then power consumption is reduced and processing speed increases, but device complexity increases due to additional routing control mechanisms
Solution Approach 1:
The crossbar architecture employs self-service routing mechanisms where the weight matrix itself encodes routing information. The sparsity pattern of weights automatically guides data flow to appropriate processors without requiring complex external control logic, thereby reducing overall system complexity despite the advanced routing capabilities.
Solution Approach 2:
The crossbar structure serves multiple functions simultaneously: it performs weight multiplication, data routing, and processor selection in a single integrated component. This multi-functionality reduces the need for separate control mechanisms, offsetting the added complexity with functional consolidation.
Data Source
AI summary
Each processor of the SIMD array performs the computations for a respective neuron of a neural network. As part of this computation, each processor of the SIMD array multiplies an input to a weight and accumulates the result for its assigned neuron each (MAC) instruction cycle. A table in a first memory is used to store which input is fed to each processor of the SIMD array. A crossbar is used to route a specific input to each processor each MAC cycle. A second memory is used to provide the appropriate weight to each processor that corresponds the input being routed to that processor.