Neural Network Hardware Depth-Wise Block Processing
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Solution Overview
Problem
Deep Neural Networks (DNNs) face challenges in efficient hardware implementation due to limited power resources and silicon area, requiring configurations that reduce processing power and silicon area while supporting various DNN configurations.
Innovation Solution
A hardware implementation of a neural network processes input data in blocks depth-wise through multiple layers, using one or more memory devices to evaluate all layers for a given block before moving to the next, reducing memory-access overhead and enabling efficient processing by exploiting overlapping data dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DNNs are implemented in hardware with limited resources, then power consumption and silicon area are reduced, but processing capabilities and flexibility are limited
Solution Approach 1:
The patent segments the neural network computation into blocks of input data that are processed depth-wise through multiple layers. This segmentation allows the hardware to process smaller chunks of data sequentially through the network depth, reducing the memory bandwidth requirements and power consumption while maintaining the ability to handle different DNN configurations through reconfigurable processing elements.
Solution Approach 2:
The patent employs dynamic resource allocation where the same hardware resources are reused across different layers and blocks of data. The processing elements are dynamically reconfigured to handle different DNN architectures, layer types, and data formats, enabling flexible adaptation without requiring dedicated hardware for each configuration.
2Area of stationary object
If DNNs are implemented in hardware with limited resources, then silicon area is reduced, but processing capabilities are limited
Solution Approach 1:
The patent merges multiple processing functions into shared hardware resources. The same processing elements, memory structures, and control logic are reused across different layers and computational blocks, eliminating the need for dedicated hardware instances for each layer. This merging significantly reduces silicon area while maintaining full processing capability through time-multiplexed resource utilization.
Solution Approach 2:
The patent designs universal processing elements that can perform multiple functions depending on the configuration. These processing elements can handle different types of neural network operations (convolution, fully connected, activation functions) and can be reconfigured via software control to match the specific requirements of different DNN architectures, providing high processing capability within limited silicon area.
3Loss of energy
If memory-access overhead is reduced by processing blocks depth-wise, then energy consumption is reduced, but memory bandwidth requirements are reduced
Solution Approach 1:
The patent loads entire blocks of input data into on-chip memory buffers before processing begins. This preliminary action ensures that all necessary data for a complete depth-wise pass through the network is available in fast on-chip memory, eliminating the need for repeated off-chip memory accesses during processing and significantly reducing both energy consumption and memory bandwidth requirements.
Data Source
AI summary
A hardware implementation of a neural network and a method of processing data in such a hardware implementation are disclosed. Input data for a plurality of layers of the network is processed in blocks, to generate respective blocks of output data. The processing proceeds depth-wise through the plurality of layers, evaluating all layers of the plurality of layers for a given block, before proceeding to the next block.