Multi-Processor Neural Network Engine Redundancy Check

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current self-test mechanisms for multi-processor neural network processing apparatuses in automotive systems face challenges in achieving high safety coverage without excessive silicon area and power consumption, as existing redundancy methods are costly and software-based Built-in Self-Test (BIST) provides limited coverage and affects performance.

Innovation Solution

Implementing a multi-processor neural network processing apparatus that allows each processing engine to run a configuration independently and then in redundant mode, comparing results to identify faults, with a CPU managing redundancy checks across clusters to minimize resource usage and maintain system functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundancy mechanism is used to ensure ASIL-D safety, then safety coverage is improved, but silicon area and power consumption increase significantly

Engineering Contradiction:
Improvesafety coverageVSAvoidsilicon area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The system dynamically switches between operational mode and self-test mode. Processing engines that would otherwise be idle are temporarily allocated to perform redundancy checks on active engines, rather than maintaining permanent duplicate hardware. This dynamic resource allocation achieves ASIL-D safety coverage without the continuous silicon area and power overhead of static redundancy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The operational processing engine performs self-testing by executing the same configuration on an idle engine and comparing results. The system uses its own operational resources to conduct safety verification, eliminating the need for separate dedicated test hardware. The engine serves both its primary function and its own safety verification needs through time-multiplexed operation.

Inventive Principle:
Principle #25Self-service

2Reliability

If hardware BIST circuitry is added to processing accelerators, then verification coverage is improved, but silicon area increases approaching redundancy limits

Engineering Contradiction:
Improveverification coverageVSAvoidsilicon area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The processing engines are designed to perform multiple functions: primary neural network processing and safety verification through redundancy checks. The same engine hardware that processes neural network configurations also serves as a test engine for verifying other engines' correctness. This multi-functionality eliminates the need for separate dedicated BIST circuitry, achieving high verification coverage without additional silicon area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If software BIST is implemented to test processing accelerators, then ease of implementation is improved, but verification coverage remains low and performance is affected

Engineering Contradiction:
Improveimplementation easeVSAvoidverification coverage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system implements dynamic mode switching between operational mode and self-test mode. During self-test mode, idle processing engines execute test configurations from the active engine and compare results. This dynamic approach enables comprehensive hardware verification that goes beyond typical software BIST capabilities while maintaining ease of implementation through software-controlled mode transitions and configuration management.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3668015B1A multi-processor neural network processing apparatus
Publication Date: 2021.04.14 FOTONATION LIMITED
  • EP3668015B1 patent drawingFigure 1
  • EP3668015B1 patent drawingFigure 2
  • EP3668015B1 patent drawingFigure 3

AI summary

A multi-processor neural network processing apparatus comprises: a plurality of network processing engines, each for processing one or more layers of a neural network according to a network configuration. A memory at least temporarily stores network configuration information, input image information, intermediate image information and output information for the network processing engines. At least one of the network processing engines is configured, when otherwise idle, to identify configuration information and input image information to be processed by another target network processing engine and to use the configuration information and input image information to replicate the processing of the target network processing engine. The apparatus is configured to compare at least one portion of information output by the target network processing engine with corresponding information generated by the network processing engine to determine if either the target network processing engine or the network processing engine is operating correctly.