Neural Network Chip Floorplan Generation
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Solution Overview
Problem
Conventional floorplanning solutions for computer chip design require extensive human involvement and consume significant computational resources, making it difficult to generate high-quality chip floorplans efficiently.
Innovation Solution
The use of a node placement neural network trained through reinforcement learning to automatically generate high-quality chip floorplans with minimal user involvement, optimizing metrics such as area, wire length, and congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional automated floorplanning approaches are used, then computational power and wall clock time are consumed, but high-quality floorplans cannot be reliably generated without excessive resources
Solution Approach 1:
The patent replaces conventional automated floorplanning algorithms with a neural network-based system trained through reinforcement learning. The neural network learns optimal placement strategies through self-play training, substituting traditional computational optimization methods with a learned policy that can generate high-quality floorplans more efficiently.
Solution Approach 2:
The system performs preliminary training of the neural network through extensive self-play before actual floorplan generation. This preliminary action allows the network to learn optimal strategies in advance, enabling it to generate high-quality floorplans during deployment without requiring excessive computational resources during the actual placement process.
2Manufacturing precision
If conventional floorplanning methods are used, then human expert involvement is required, but the process takes weeks and consumes significant resources
Solution Approach 1:
The neural network is trained through self-play, where it learns to generate optimal floorplans by playing against itself during the training phase. This self-service mechanism eliminates the need for human expert involvement during both training and deployment, allowing the system to autonomously learn and generate high-quality floorplans without human intervention.
Solution Approach 2:
The patent substitutes human expert knowledge with a neural network that has been trained through reinforcement learning. The network captures expert-level floorplanning skills in its learned policy, replacing the need for human experts while dramatically reducing the time required from weeks to minutes or hours.
3Manufacturing precision
If the number of potential node placement combinations is explored exhaustively, then optimal placement may be found, but computational resources become excessive
Solution Approach 1:
The patent changes the approach from exhaustive search of placement combinations to a learned policy that directly predicts optimal placements. By transforming the problem from combinatorial optimization to pattern recognition through reinforcement learning, the system achieves optimal placement without exploring the exponential space of possible configurations.
Solution Approach 2:
The system replaces exhaustive combinatorial search with a neural network-based prediction system. The network learns the mapping from floorplan specifications to optimal placements through self-play training, substituting brute-force exploration with intelligent prediction that achieves optimal results with polynomial computational complexity.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.