Neural Network Hardware Acceleration Parsing Module
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Solution Overview
Problem
Existing hardware acceleration apparatuses for neural network computations lack versatility due to specialization in specific network structures, limiting their applicability to various types and scales of neural network computations.
Innovation Solution
A hardware acceleration apparatus comprising a memory module, parsing module, and multiple functional modules, where the parsing module issues operation instructions based on the size of the memory module and data requirements, enabling flexible operation and acceleration of neural network computations by disassembling computations into sub-computations and managing data and storage efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware acceleration apparatus is fully specialized for certain particular network structures, then computation efficiency is improved, but versatility deteriorates
Solution Approach 1:
The patent designs a hardware acceleration apparatus that can perform multiple types of neural network computations (convolutional neural networks, recurrent neural networks, fully connected neural networks) using the same physical hardware. The parsing module interprets different computation types and routes them to appropriate functional modules, enabling one hardware system to serve multiple purposes without sacrificing computation efficiency for any specific network type.
Solution Approach 2:
The hardware acceleration apparatus is divided into multiple functional modules (convolutional computation module, matrix multiplication module, activation computation module, pooling computation module) that can be selectively activated. The parsing module segments the instruction sequence into different operation types and directs them to corresponding functional modules, allowing the system to maintain specialized computation paths for each network type while using a unified hardware architecture.
2Productivity
If hardware acceleration apparatus is designed for large-scale neural network computations, then computation capability is improved, but adaptability to different models deteriorates
Solution Approach 1:
The patent implements dynamic configuration of hardware resources through the parsing module, which can adaptively allocate computational tasks to different functional modules based on the specific neural network model being executed. The system dynamically adjusts which functional modules are active and how data flows through the system, allowing large-scale computations to be performed while maintaining flexibility to accommodate different model architectures and sizes.
Solution Approach 2:
The hardware acceleration apparatus allows parameter changes in the parsing module that can adjust the behavior and configuration of functional modules based on the specific computation requirements. By changing operational parameters and instruction interpretation rules, the system can optimize for different model types and scales without requiring physical hardware changes.
Data Source
AI summary
Disclosed are a hardware acceleration apparatus and an acceleration method for neural network computing. The hardware acceleration apparatus comprises a memory module, a parsing module and a plurality of functional modules, wherein the memory module is used for caching data required by neural network computing; the parsing module is used for receiving an instruction sequence that is predetermined according to the size of the memory module and the data required by neural network computing, for parsing the instruction sequence so as to obtain a plurality of types of operation instructions, and for issuing a corresponding type of operation instruction to each functional module; and each functional module is used for executing a corresponding operation of neural network computing in response to the reception of the corresponding type of operation instruction. By using the hardware acceleration apparatus for neural network computing, the universality of the hardware acceleration apparatus can be improved.